### Table I Comparison of Petri Net models and analysis of four ACM algorithms

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### Table 1: Design statistics for three industrial circuits.

2001

"... In PAGE 2: ... For analysis, three industrial circuit designs are used. The properties of the designs are given in Table1 . The active intervals are calcu- lated during three stages of the design flow: (i) the pre-placement stage on which delays are calculated using wireload model, (ii) the post-placement stage on which net delays are estimated based on the half-perimeter bounding box of the net, and (iii) the post-routing stage.... ..."

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### Table 1: Design statistics for three industrial circuits.

2001

"... In PAGE 2: ... For analysis, three industrial circuit designs are used. The properties of the designs are given in Table1 . The active intervals are calcu- lated during three stages of the design flow: (i) the pre-placement stage on which delays are calculated using wireload model, (ii) the post-placement stage on which net delays are estimated based on the half-perimeter bounding box of the net, and (iii) the post-routing stage.... ..."

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### Table I. Energy Consumption (nJ) of all the multiplier circuits with varying bit lengths and adders for a 180 nm BPTM Mosfet Model.

2005

### Table II. Multiplier Delay Performance (ns) of all the multiplier circuits with varying bit lengths and adders for 180 nm BPTM Mosfet Model.

2005

### Table III. Energy Consumption (nJ) of all the multiplier circuits with varying bit lengths and adders for a 180 nm BPTM Mosfet Model.

2005

### Table 3. Results of vector compaction for different benchmark circuits.

2005

"... In PAGE 8: ... The algorithm was implemented and the fault coverage was observed to be the same as SS. A reduction in test vectors up to 60% can be observed ( Table3 ) in most of the circuits. Maximum reduction is achieved when the average number of faults per combinational vector is small and the number of flip-flops is proportionally higher.... In PAGE 8: ... This is because of the improvement that we made in the design, by minimizing the number of signals that needs to be routed to every flip-flop. The increase in number of gates over SS is between 6%-11% ( Table3 ). Relative reduction of power dissipation in the circuit is calculated assuming that, the power dissipated is directly proportional to the number of transitions in the primary inputs and states of flip-flops.... ..."

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### Table 2 reports a compact analysis of such proposal for a first order model of the design costs. It depicts the breakeven under different environmental conditions, i.e. the number of uses making valuable designing for reuse (CostCoef=1).

"... In PAGE 3: ... Table2 . Analysis of the Breakeven conditions, NS stands for no-Solution.... ..."

### Table 1. Capacitor and (first order) Mosfet models.

2006

"... In PAGE 2: ... For example, capacitance is the parameter for a capacitor and width and length parameterize a mosfet. Models to express the behavior of capacitors and mos- fets are shown in Figure 1 and Table1 . Here, the mosfet model is inaccurate (a first order approximation).... ..."

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