### Table 3: Grid reduction and CPU times for transient analysis. Design Exact transient time MG transient time

"... In PAGE 7: ... As explained earlier, the proposed multigrid-like technique is even more advantageous when applied for transient analysis. This is illustrated in Table3 , which shows the time required to run a transient simulation of the power grids of the two designs using a regular solver and the proposed technique. The power grids are simulated for a duration of 4 ns with 0.... ..."

### Table 3: Grid reduction and CPU times for transient analysis. Design Exact transient time MG transient time

"... In PAGE 7: ... As explained earlier, the proposed multigrid-like technique is even more advantageous when applied for transient analysis. This is illustrated in Table3 , which shows the time required to run a transient simulation of the power grids of the two designs using a regular solver and the proposed technique. The power grids are simulated for a duration of 4 ns with 0.... ..."

### Table 3: Grid reduction and CPU times for transient analysis. Design Exact transient time MG transient time

"... In PAGE 7: ... As explained earlier, the proposed multigrid-like technique is even more advantageous when applied for transient analysis. This is illustrated in Table3 , which shows the time required to run a transient simulation of the power grids of the two designs using a regular solver and the proposed technique. The power grids are simulated for a duration of 4 ns with 0.... ..."

### Table 5. Fault simulation results for transient analysis of BJT differential amplifier

"... In PAGE 5: ... For transient analysis, the accuracy of fault collapsing is compared using the difference between the fault-free circuit and faulty circuits on the whole range of analysis = - = T t f t t f T 1 0 1 x x e . Table5 lists the results for the differential amplifier simulated for 100 m s. The second column shows the greatest instantaneous difference between the faulty and fault-free circuits over the whole simulation period.... ..."

### Table Models for Timing Simulation. In Proceedings of the 1984 Custom Integrated Circuits Conference. May, 1984. [Subramaniam 85-1 P. Subramaniam. Modeling MOS VLSI Circuits for Transient Analysis. IEEE Joumal of Solid-State Circuits vol. SC-21(2), April, 1985.

1987

### TABLE III Grid reduction and CPU times for transient analysis.

2002

Cited by 30

### TABLE III Grid reduction and CPU times for transient analysis.

### Table 3. Transient analysis results. Circuit 1 Circuit 2 Circuit 3

2005

"... In PAGE 6: ... Perfect voltage sources are connected to 1% of their nodes at random locations, and current sources have a random-size peak at a random time range. The results of our approach are shown in Table3 . The CPU times shown correspond to the runtimes for the time steps that follow the initial DC analysis and the first transient step.... ..."

Cited by 7

### Table 3.1. Reduction of the number of fault pairs Circuit % Reduction

### Table 4.1: Reduction in the Number of Faults Circuit Orig. Num of Faults Maximum faults Reduction

2003