Abstract—Device scaling and large-scale integration have led to growing concerns about soft errors in microprocessors. To date, in all but the most demanding applications, implementing parity and ECC for caches and other large, regular SRAM structures have been sufficient to stem the growing soft

of transient faults in QDI circuits and describe the causes that lead the faults to be memorized into one or more soft errors. Therefore, a refined fault sensitivity criterion is defined for this class of circuits. This methodology enables us to point out the weak parts of a circuit. An analysis tool

quantify and identify the sources of ACE analysis conservatism by comparing an ACE analysis methodology against a rigorous fault-injection study. We evaluate two flavors of ACE analysis: a “simple ” analysis and a refined analysis, finding that even the refined analysis overestimates the soft error

techniques using recursive structures for the implementation of moving average filters that provide protection against Single Event Upsets are evaluated through two fault injection systems based on simulation and emulation respectively. Fault injection campaigns show that system knowledge-based redundancy

Abstract—In nowadays technologies, circuits are more and more sensitive to aging phenomenon, as well as soft errors. Furthermore several attacks that used a fault to derive secret information have been demonstrated on cryptosystems. Concurrent fault detection is thus of prime interest

, using higher performance commercial hardware wherever possible. This has the potential to revolutionize onboard data processing, but it cannot happen unless the soft error reliability can be characterized and deemed sufficient. A variety of fault injection techniques are used to evaluate system

Tracker soft-ware system is presented. The system is shown effective through multiple proxy deploy-

ii iv vTo my parents vi vii Acknowledgements I would first and foremost extend my whole-hearted gratitude to my advisors, An-drea Arpaci-Dusseau and Remzi Arpaci-Dusseau. Andrea and Remzi are the reason that I had the opportunity for this exceptional Ph.D. journey. To this day, I still re-member the moment when they took me as their student and the joy and hope in my heart. Andrea and Remzi have showed me what systems research is like and how much fun and challenging it can be. Before this journey with them, I had always liked and believed in the beauty of mathematics and theory. My initial interest in systems research happened when I took Remzi’s Advanced Operating Systems

I first thank my thesis advisors Thiemo Voigt and Adam Dunkels for being my excellent advisors, and also for being the great colleagues you still are. Thiemo and Adam have complemented each other superbly, giving me feedback, perspectives, insights, and having made every single new venture truly fun. My deepest thanks also go to my professor Per Gunningberg, Uppsala University. Per has in a seemingly easy way spotted erroneous assumptions, has valued my research contributions, and has connected my own work with another broader world of research. I want to thank all colleagues in the Networked Embedded Systems group:

Abstract—This paper highlights and characterizes the main obstacle to deploying a robust wireless sensor network testbed: the USB connections that link each of the nodes via ethernet gateways to the central server. Unfortunately, these connections are also the components that, when properly installed, can reduce testbed costs by attaching multiple nodes per gateway. After illustrating how unreliable current solutions can become (regardless of the used sensor nodes, USB cabling, or gateway setup), a set of experiments led to a list of dos and don’ts in testbed deployment. Furthermore, a simple and cost-effective suggestion is presented that allows to bypass current USB backchannel issues, leading to a more robust testbed that avoids manual maintenance of individual nodes. Index Terms—experimentation; testbeds; testbed reliability; sensor node reprogramming; universal serial bus I.