### Table 1: Comparison of interconnection networks, assuming full-duplex bidirectional data channels.

"... In PAGE 3: ... Figure 1 shows examples of 2-D HOW systems. Table1 compares the numbers of channels in the binary hypercube (i.e.... ..."

### Table 2: Packet Duration Times for Full-Duplex Ethernet

2002

"... In PAGE 2: ...annot be transmitted back-to-back. The IEEE specification calls this parameter the interFrameGap. While not defined in terms of bit times, interFrameGap happens to be 96 bit times in duration for 10Mb/s, 100Mb/s, and 1Gb/s Ethernet. Table2 lists the durations (in bit times) for the minimum and maximum packet sizes. From this table we see, for example, that the time from the start of a minimum sized packet to the start of the next packet is 672 bit times.... ..."

Cited by 7

### Table 1 Description of a host processor. 2. in full-duplex mode,

### Table 1. Level of misrouting for the full-duplex and half-duplex chaos networks at full load.

"... In PAGE 6: ...Table1 shows the level of misrouting at saturation for each traffic pattern under the two network configurations. Note that each time a packet is derouted, its path increases by 2 hops.... ..."

### Table 1: Matrix multiplication parameters. Reuse Self-Interference Footprint References

1991

"... In PAGE 4: ... Since the variable X[i,j] is allocated to a register, the total number of references to elements of the array is 78 36166 and its miss rate is simply 0. Substituting the parameters in Table1 into Equation 2, the miss rates for Y and Z, 7740 89 41 and 7740 9041 , are 7740 89 41 61 1 0 0 1 0 83 105 40 89 41 1 16 1 0 266 67 1716 1 0 66 67 17 25 83 105 40 89 4143 3 0 1 0 83 105 40 89 41 1 66 67 7740 90 41 61 1 0 16 1 0 1 67 1716 1 0 66 67 17 25 66 67 The total number of cache misses are therefore 78 3 66 43 78 3 16 1 78 43 78 0 1 78 7740 89 41 17 43 78 3 16 1 66 43 66 0 1 66 7740 90 41 17 25 78 3 32 2 66 43 83 105 40 89 4143 3 0 1 0 83 105 40 89 41 1 66 67 43 66 67 33 40 341 According to this equation, there are 278 36166intrinsic misses, misses that are intrinsic to the algorithm given the blocking factor and cannot be avoided even if the address mapping is perfect. The factor 83 105 40 89 41 is due to self interference of variable Y on itself.... ..."

Cited by 514

### Table 1: Matrix multiplication parameters. Reuse Self-Interference Footprint References

"... In PAGE 4: ... Since the variable X[i,j] is allocated to a register, the total number of references to elements of the array is 7836166 and its miss rate is simply 0. Substituting the parameters in Table1 into Equation 2, the miss rates for Y and Z, 774089 41 and 77409041, are 774089 41 61 1 0 01 0 831054089 411161 0 266 67 17161 0 66 67 17 25 831054089 41 43 3 01 0 831054089 41166 67 77409041 61 1 0 161 0 1 67 17 161 0 6667 17 25 66 67 The total number of cache misses are therefore 783 66 43 783 16 1 78 43 78 0 1 78 774089 4117 43 783 16 1 66 43 66 0 1 66 7740904117 25 783 32 2 66 43 831054089 41 43 3 01 0 831054089 41166 67 43 6667 33 40341 According to this equation, there are 278 36166 intrinsic misses, misses that are intrinsic to the algorithm given the blocking factor and cannot be avoided even if the address mapping is perfect. The factor 831054089 41 is due to self interference of variable Y on itself.... ..."

### Table 12: Number of writes that self-interfere after removing unused indices

1992

"... In PAGE 86: ... This is equivalent to checking for an output memory disambiguation dependence from the write to itself with a non-0 direction vector component. Table12 shows that after removing the unused... ..."

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### Table B.1: QSTBC members with real-valued channel dependent self-interference parameter X.

2005

### Table B.2: QSTBC members with imaginary valued channel dependent self-interference parameter X.

2005

### Table IV. Blocks with No Self- Interference (from our algorithm)

1999

Cited by 111