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SAT-based semiformal verification of hardware

by Sabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, Er Nadel - PROCEEDINGS OF THE 10TH INTERNATIONAL CONFERENCE ON FORMAL METHODS IN COMPUTERAIDED DESIGN (FMCAD , 2010
"... Semiformal, or hybrid, verification techniques are extensively used in pre-silicon hardware verification. Most approaches combine simulation and formal verification (FV) algorithms to achieve better design coverage than conventional simulation and scale better than FV. In this paper we introduce a ..."
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purely SAT-based semiformal verification (SFV) method that is based on new algorithms for generating multiple heterogeneous models for a propositional formula. An additional novelty of our paper is the extension of the SFV algorithm to liveness properties. The experimental data presented in this paper

Generating diverse solutions in SAT

by Alexander Nadel - Theory and Applications of Satisfiability Testing - SAT 2011, 14th International Conference, Ann Arbor , 2011
"... Abstract. This paper considers the DiversekSet problem in SAT, that is, the problem of efficiently generating a number of diverse solutions (satisfying assignments) given a propositional formula. We provide an extensive analysis of existing algorithms for this problem in a newly developed framework ..."
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quality of the solutions on large industrial instances of DiversekSet arising in SAT-based semiformal verification of hardware. 1

Strategies for SAT-based Formal Verification

by Vishnu C. Vimjam, Dr. Ezra Brown, Basavaiah Naidu, Vishnu C. Vimjam , 2007
"... Verification of digital hardware designs is becoming an increasingly complex task as the designs are incor-porating more functionality, becoming complex and growing larger in size. Today, verification remains a bottleneck in meeting time-to-market requirements and consumes more than 70 % of the over ..."
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verification, which has gained tremendous importance in the recent past. Importantly, SAT-based approaches often alleviate the mem-ory explosion problem, which had been a bottleneck of the traditional symbolic (Binary Decision Diagram

Symbolic Model Checking Using SAT Procedures instead of BDDs

by A. Biere, A. Cimatti, E. M. Clarke, M. Fujita, Y. Zhu - DAC 99 , 1999
"... In this paper, we study the application of propositional decision procedures in hardware verification. In particular, we apply bounded model checking, as introduced in [1], to equivalence and invariant checking. We present several optimizations that reduce the size of generated propositional formula ..."
Abstract - Cited by 329 (28 self) - Add to MetaCart
formulas. In many instances, our SAT-based approach can significantly outperform BDD-based approaches. We observe that SAT-based techniques are particularly efficient in detecting errors in both combinational and sequential designs.

SAT-based methods for sequential hardware equivalence verification without synchronization

by Zurab Khasidashvili, Ziyad Hanna - Electronic Notes in Theoretical Computer Science , 2003
"... The BDD- and SAT-based model checking and verification methods normally require an initial state. Here we are concerned with sequential hardware verification, where an initial state must be one of the reset states. In practice, a reset state is not always given by the designer, and computing a reset ..."
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The BDD- and SAT-based model checking and verification methods normally require an initial state. Here we are concerned with sequential hardware verification, where an initial state must be one of the reset states. In practice, a reset state is not always given by the designer, and computing a

SAT-based Sequential Depth Computation

by unknown authors
"... Abstract – Determining the depth of sequential circuits is a crucial step towards the completeness of bounded model checking proofs in hardware verification. In this paper, we formulate sequential depth computation as a logical inference problem for Quantified Boolean Formulas. We introduce a novel ..."
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technique to simplify the complexity of the constructed formulas by applying simple transformations to the circuit netlist. We also study the structure of the resulting simplified QBFs and construct an efficient SAT-based algorithm to check their satisfiability. We report promising experimental results

Demonstration of Hardware-Accelerated Formal Verification

by Hiroaki Yoshida, Satoshi Morishita Masahiro Fujita
"... Abstract—A semi-formal verification technique, which performs a brute-force compiled simulation with a sophisticated search space pruning, has been proposed and shown to be competitive with the state-of-the-art SAT-based verification techniques [1]. This paper presents a novel approach for accelerat ..."
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Abstract—A semi-formal verification technique, which performs a brute-force compiled simulation with a sophisticated search space pruning, has been proposed and shown to be competitive with the state-of-the-art SAT-based verification techniques [1]. This paper presents a novel approach

Circuit Partitioning for SAT-based Combinational Circuit Verification -- A Case Study

by Marc Herbstritt, Thomas Kmieciak, Bernd Becker , 2004
"... Hardware verification is nowadays one of the most time-consuming tasks during chip design. In the last few years SAT-based methods have become a core technology in hardware design, especially for the verification of combinational parts of the circuits. Verifying the equivalence of some specification ..."
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Hardware verification is nowadays one of the most time-consuming tasks during chip design. In the last few years SAT-based methods have become a core technology in hardware design, especially for the verification of combinational parts of the circuits. Verifying the equivalence of some

ENHANCING SAT-BASED FORMAL VERIFICATION METHODS USING GLOBAL LEARNING

by Rajat Arora, Rajat Arora , 2004
"... With the advances in VLSI and System-On-Chip (SOC) technology, the complexity of hardware systems has increased manifold. Today, 70 % of the design cost is spent in verifying these intricate systems. The two most widely used formal methods for design verification are Equivalence Checking and Model C ..."
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SAT-based Combinational Equivalence Checking (CEC) and Bounded Model Checking (BMC). The idea is to perform a low-cost preprocessing that will statically induce global signal relationships into the original CNF formula of the circuit under verification and hence reduce the complexity of the SAT

A Hybrid SAT-Based Decision Procedure for Separation Logic with Uninterpreted Functions

by Sanjit A. Seshia, Shuvendu K. Lahiri, Randal E. Bryant - In Proc. DAC’03 , 2003
"... SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on encoding atomic subformulas with Boolean variables, or by encoding integer variables as bit-vectors. Based on evaluating the ..."
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SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on encoding atomic subformulas with Boolean variables, or by encoding integer variables as bit-vectors. Based on evaluating
Results 1 - 10 of 91