### TABLE I QBF-BASED VERSUS SAT-BASED MODEL-FREE FAULT DIAGNOSIS

2007

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### Table 1 [a-b]. Memory amp; Performance evaluation of the distributed SAT-based BMC

"... In PAGE 11: ... We also used 3 different settings of the Ethernet switch to show how the network bandwidth affects the communication overheads. We present the results of the controlled experiments in Table1 [a-b]. In Table 1a, the 1st Column shows the set of designs (D1-D6 have a counterexam- ple), the 2nd Column shows the number of Flip Flops and 2-input Gates in the fani- cone of the safety property in the corresponding design, the 3rd Column shows the bound depth limit for analysis, the 4th Column shows the total memory used by the non-distributed BMC, the 5th Column shows the partition depth when Client C2 took an exclusive charge of the further unrolling, Columns 6-8 show the memory distribu- tion among the Master and the Clients.... In PAGE 11: ... We present the results of the controlled experiments in Table 1[a-b]. In Table1 a, the 1st Column shows the set of designs (D1-D6 have a counterexam- ple), the 2nd Column shows the number of Flip Flops and 2-input Gates in the fani- cone of the safety property in the corresponding design, the 3rd Column shows the bound depth limit for analysis, the 4th Column shows the total memory used by the non-distributed BMC, the 5th Column shows the partition depth when Client C2 took an exclusive charge of the further unrolling, Columns 6-8 show the memory distribu- tion among the Master and the Clients. In the Column 9, we calculate the scalability ratio, i.... In PAGE 12: ...Table1 b, the 1st Column shows the cumulative time taken (over all steps) by non-distributed BMC, the 2nd Column shows the cumulative time taken (start to finish of Master over all steps) by our distributed-BMC excluding the message wait time, Columns 3-5 show the total message wait time for the Master in a 10/100/1000Mbps Ethernet Switch setting. In the Column 6, we calculate the performance penalty by taking the ratio of the time taken by distributed to that of non-distributed BMC (=Para Time/ Mono Time).... ..."

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### Table 2: Minimizing Leakage with SAT- and LP- based ILP. Circuit Random Simulation GA SAT-based ILP (galena) LP-based ILP (OSL)

in Circuit-based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation

"... In PAGE 5: ... We run random simulation with 50000 vectors to obtain a bound on the leakage amount and its mean value. The corresponding results are shown in Column Random Simulation in Table2 . Furthermore, we apply a genetic algorithm [15] using 21 generations of 1000 vectors (total of 21000 vectors); the results are shown in column GA .... In PAGE 5: ... The solver is run at most 11 times for 3 seconds each then once more for 30 seconds. The best results obtained before termination are shown in columns 7 and 8 of Table2 . Provably optimal results are marked by parentheses along with the used run time.... ..."

### Table 2: Minimizing Leakage with SAT- and LP- based ILP. Circuit Random Simulation GA SAT-based ILP (galena) LP-based ILP (OSL)

in Circuit-based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation

"... In PAGE 5: ... We run random simulation with 50000 vectors to obtain a bound on the leakage amount and its mean value. The corresponding results are shown in Column Random Simulation in Table2 . Furthermore, we apply a genetic algorithm [15] using 21 generations of 1000 vectors (total of 21000 vectors); the results are shown in column GA .... In PAGE 5: ... The solver is run at most 11 times for 3 seconds each then once more for 30 seconds. The best results obtained before termination are shown in columns 7 and 8 of Table2 . Provably optimal results are marked by parentheses along with the used run time.... ..."

### Table 4. Comparison with SAT-based algorithms

### Table 3. Comparing SAT-based re-simulation with random re-simulation over a partition for generating 32 vectors. The time-out is 10000 seconds. The runtime is also shown for the entropy analysis performed.

"... In PAGE 6: ...0. In Table3 , we show that evenly simulating a partition by randomly assigning values to its inputs and checking whether the primary input constraints are satisfied, is often much slower than using SAT-guided simulation. The results indicate that the SAT-based simulation scales well for larger circuits, in part, because the size of the XOR constraints re- quired are typically small compared to the size of the circuit.... ..."

### Table 2: Runtime of depth formulas on SAT-based QBF solver

2003

"... In PAGE 12: ... Next, we report experimental results on the ISACS benchmarks when using our specialized QBF solver. The results are shown in Table2 . The name of the circuit appears in column 1.... ..."

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### TABLE I QBF-BASED VERSUS SAT-BASED BMC

### Table 3: Generated number of distinct solutions for the SAT-based metering scheme

2001

"... In PAGE 13: ... In order to test the technique in a much more demanding scenario, we applied the hardware metering scheme on the SAT problem. The experimental results are shown in Table3 . The first column indicates the name of DIMACS benchmark [12] and the middle column indicates the number of used variables.... ..."

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