### Table 3: Power consumptions for 15 classes of sets of tasks (as- signment; resources allocated).

1997

"... In PAGE 6: ... The relative performance of the new allo- cation algorithm versus the described three comparison options are given in Table 4. The experimental results for the task assignment heuristic are shown in Table3 . The table shows power consumption for 15 dif- ferent classes of sets of tasks and processors.... ..."

Cited by 34

### Table 3: Power consumptions for 15 classes of sets of tasks (as- signment; resources allocated).

"... In PAGE 6: ... The relative performance of the new allo- cation algorithm versus the described three comparison options are given in Table 4. The experimental results for the task assignment heuristic are shown in Table3 . The table shows power consumption for 15 dif- ferent classes of sets of tasks and processors.... ..."

### Table 1. Parameters used in QualNet and OFDM simulation.

in Abstract

"... In PAGE 5: ... With different seeds, the node placement and CBR sessions in the network differ. Other common parameters are listed in Table1 . The transmission power and receiver sensitivity are taken from [19], an actual commercial implementation of the IEEE 802.... ..."

### Table 2: Minimizing Area vs. Minimizing Power

1995

"... In PAGE 4: ...Lastly, for circuit comp,we presentin Table2 the circuitarea and the correspondingpower #28per cycle#29, for the case where the objective is to minimize the circuit area, and the case where the objective is to minimize the power, under various delay spec- i#0Ccations. Since the minimum power circuit corresponds to a delay of 220.... ..."

Cited by 1

### Table 2: Results on Power Minimization

"... In PAGE 4: ...During power minimization, we initially use SIS [8] to optimize the circuits for area and MED [6] to obtain the transition density of each gate. The results are shown in Table2 . Column 1 contains the circuit name and col- umn 2 has the number of transformations our algorithm performs on every circuit.... In PAGE 4: ... To include delay consideration, we can modify our algorithm to disre- gard logic transformations that reduce the power but increase the delay, as described in [7] [12]. The final column of Table2 contains the CPU run-time. As with the case of delay optimization, we expect that as more heuristics are developed the results will improve significantly.... ..."

### Table 2: Results on Power Minimization

"... In PAGE 4: ...During power minimization, we initially use SIS [8] to optimize the circuits for area and MED [6] to obtain the transition density of each gate. The results are shown in Table2 . Column 1 contains the circuit name and col- umn 2 has the number of transformations our algorithm performs on every circuit.... In PAGE 4: ... To include delay consideration, we can modify our algorithm to disre- gard logic transformations that reduce the power but increase the delay, as described in [7] [12]. The final column of Table2 contains the CPU run-time. As with the case of delay optimization, we expect that as more heuristics are developed the results will improve significantly.... ..."

### Table III Power minimization results

### TABLE I SINR and power allocation.

2003

Cited by 15