Results 1 - 10
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137
Faster Secure Two-Party Computation Using Garbled Circuits
- In USENIX Security Symposium
, 2011
"... Secure two-party computation enables two parties to evaluate a function cooperatively without revealing to either party anything beyond the function’s output. The garbled-circuit technique, a generic approach to secure two-party computation for semi-honest participants, was developed by Yao in the 1 ..."
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Cited by 121 (22 self)
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that is significantly faster than any previously reported while also scaling to arbitrarily large circuits. We validate our approach by demonstrating secure computation of circuits with over 10 9 gates at a rate of roughly 10 µs per garbled gate, and showing order-of-magnitude improvements over the best previous
Efficient secure computation with garbled circuits
- In ICISS
, 2011
"... Abstract. Secure two-party computation enables applications in which partic-ipants compute the output of a function that depends on their private inputs, without revealing those inputs or relying on any trusted third party. In this pa-per, we show the potential of building privacy-preserving applica ..."
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Cited by 7 (0 self)
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applications using gar-bled circuits, a generic technique that until recently was believed to be too ineffi-cient to scale to realistic problems. We present a Java-based framework that uses pipelining and circuit-level optimizations to build efficient and scalable privacy-preserving applications. Although
Two Halves Make a Whole: Reducing Data Transfer in Garbled Circuits using Half Gates
, 2014
"... The well-known classical constructions of garbled circuits use four ciphertexts per gate, although various methods have been proposed to reduce this cost. The best previously known methods for optimizing AND gates (two cipher-texts; Pinkas et al., ASIACRYPT 2009) and XOR gates (zero ciphertexts; Kol ..."
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Cited by 9 (3 self)
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The well-known classical constructions of garbled circuits use four ciphertexts per gate, although various methods have been proposed to reduce this cost. The best previously known methods for optimizing AND gates (two cipher-texts; Pinkas et al., ASIACRYPT 2009) and XOR gates (zero ciphertexts
Fully Key-Homomorphic Encryption, Arithmetic Circuit ABE, and Compact Garbled Circuits
, 2014
"... We construct the first (key-policy) attribute-based encryption (ABE) system with short secret keys: the size of keys in our system depends only on the depth of the policy circuit, not its size. Our constructions extend naturally to arithmetic circuits with arbitrary fan-in gates thereby further redu ..."
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Cited by 19 (2 self)
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reducing the circuit depth. Building on this ABE system we obtain the first reusable circuit garbling scheme that produces garbled circuits whose size is the same as the original circuit plus an additive poly(λ, d) bits, where λ is the security parameter and d is the circuit depth. Save the additive poly
Whitewash: Outsourcing Garbled Circuit Generation for Mobile Devices
"... Garbled circuits offer a powerful primitive for computation on a user’s personal data while keeping that data private. Despite recent improvements, constructing and evaluating circuits of any useful size remains expensive on the limited hardware resources of a smartphone, the primary computational d ..."
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Cited by 5 (1 self)
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Garbled circuits offer a powerful primitive for computation on a user’s personal data while keeping that data private. Despite recent improvements, constructing and evaluating circuits of any useful size remains expensive on the limited hardware resources of a smartphone, the primary computational
Private Set Intersection: Are Garbled Circuits Better than Custom Protocols?
, 2012
"... Cryptographic protocols for Private Set Intersection (PSI) are the basis for many important privacy-preserving applications. Over the past few years, intensive research has been devoted to designing custom protocols for PSI based on homomorphic encryption and other public-key techniques, apparently ..."
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Cited by 49 (7 self)
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due to the belief that solutions using generic approaches would be impractical. This paper explores the validity of that belief. We develop three classes of protocols targeted to different set sizes and domains, all based on Yao’s generic garbled-circuit method. We then compare the performance of our
Fault Dictionary Size Reduction for Million-Gate Large Circuits
"... Abstract- In general, fault dictionary is prevented from practical applications for its extremely large size. Several previous works are proposed for the fault dictionary size reduction. However, they might not be able to handle today’s million-gate circuits due to the high time and space complexity ..."
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complexity. In this paper, we propose an algorithm to significantly reduce the size of fault dictionary while still preserving high diagnostic resolution. The proposed algorithm possesses extremely low time and space complexity by avoiding constructing the huge distinguishability table, which inevitably
Circuit Structures for Improving Efficiency of Security and Privacy Tools
"... Abstract—Several techniques in computer security, including generic protocols for secure computation and symbolic execution, depend on implementing algorithms in static circuits. Despite substantial improvements in recent years, tools built using these techniques remain too slow for most practical u ..."
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Cited by 9 (1 self)
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uses. They require transforming arbitrary programs into either Boolean logic circuits, constraint sets on Boolean variables, or other equivalent representations, and the costs of using these tools scale directly with the size of the input circuit. Hence, techniques for more efficient circuit
Using Gate Sizing to Reduce Glitch Power
- in Proc. of the ProRISC Workshop on Circuits, Systems and Signal Processing, (Mierlo, The
, 1996
"... We propose to size gates for minimum circuit power dissipation while balancing path delays in the circuit. Delay balancing using the filtering effect of CMOS-gates avoids superfluous transitions (glitches) resulting in power saving and increased circuit reliability. The transition densities in a del ..."
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Cited by 13 (0 self)
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We propose to size gates for minimum circuit power dissipation while balancing path delays in the circuit. Delay balancing using the filtering effect of CMOS-gates avoids superfluous transitions (glitches) resulting in power saving and increased circuit reliability. The transition densities in a
Generalized universal circuits for secure evaluation of private functions with application to data classification
- In ICISC’08, volume 5461 of LNCS
, 2008
"... Abstract. Secure Evaluation of Private Functions (PF-SFE) allows two parties to compute a private function which is known by one party only on private data of both. It is known that PF-SFE can be reduced to Secure Function Evaluation (SFE) of a Universal Circuit (UC). Previous UC constructions only ..."
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Cited by 16 (8 self)
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simulated circuits with gates of d = 2 inputs while gates with d>2 inputs were decomposed into many gates with 2 inputs which is inefficient for large d as the size of UC heavily depends on the number of gates. We present generalized UC constructions to efficiently simulate any circuit with gates of d
Results 1 - 10
of
137