### Table 3. Number of clock cycles required to compute kP over GF(2m)

2000

"... In PAGE 12: ...Table3 approximates the number of cycles required for the computation of point multiplication for arbitrary GF(2m) fields. The approximations are based exclusively on the number of multiplications and the number of clock cycles required to compute them with an LSD multiplier with digit size D.... ..."

Cited by 43

### Table 3. Number of clock cycles required to compute kP over GF(2m)

"... In PAGE 12: ...Table3 approximates the number of cycles required for the computation of point multiplication for arbitrary GF(2m) elds. The approximations are based exclusively on the number of multiplications and the number of clock cycles required to compute them with an LSD multiplier with digit size D.... ..."

### TABLE 1. KEY PARAMETERS FOR DIFFERENT ARCHITECTURES OF SERIAL GF(2M) MULTIPLIERS USING DIFFERENT BASES

### Table 4: Timings (in seconds) for inversion with MT-X in GF(2m).

"... In PAGE 17: ... the inversion. A series of experimental results are presented in Table4 where MT-X denotes the X-input Montgomery trick. Each data set is organized in two rows.... In PAGE 17: ...Table 4: Timings (in seconds) for inversion with MT-X in GF(2m). As shown in Table4 , the timing improvement is negligible while exceeding MT-16. Therefore, the 16-input Montgomery trick was used in the point addition program.... ..."

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### Table 1. Complexity of point multiplication in GF(2m)(a; b 6 =0)

"... In PAGE 4: ... gt;From Table1 it is clear that an efficient method for squaring will have a con- siderable impact on the overall performance. Through the use of reconfigurable hardware it is possible to compute a square in one clock cycle for any field or- der even though a standard basis representation is being used.... In PAGE 12: ...7 times faster than the traditional double-and-add algorithm. One can deduce from Table1 that this is a direct result of the number of mul- tiplications required by each algorithm ( 10:5=6), as the processing time for additions, squares, and inversions is almost negligible. Table 4 also shows that the speedup increases as the digit size increases.... ..."

### Table 1: Probabilistic ranking for the queries

2004

"... In PAGE 6: ...e., car, tank, and rocket) are shown in Table1 , as well as their rankings, computed by the mixture models. The first column in Table 1 indicates the query group and the model it comes from, the second column in- dicates the circular shift applied (i.... In PAGE 6: ...he query results for three of our models (i.e., car, tank, and rocket) are shown in Table 1, as well as their rankings, computed by the mixture models. The first column in Table1 indicates the query group and the model it comes from, the second column in- dicates the circular shift applied (i.e.... In PAGE 6: ... Fig. 3 shows the verification re- sults for the hypotheses listed in Table1 in the case of the rocket model. We received extremely small MSE errors in all of our experiments using artificial data sets.... In PAGE 6: ... We received extremely small MSE errors in all of our experiments using artificial data sets. Table1 shows that the hypotheses with the high- est probabilities were also the correct hypotheses in all cases except in one case (i.... ..."

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### Table 1. Integer variables used in the probabilistic timed automata

2003

"... In PAGE 9: ... We suppose that the concrete host can send a packet to all the abstract hosts at the same time and only one of the abstract hosts can send a packet to the concrete host at a time. The set of variables of our probabilistic timed automata includes both clocks (x, y and z) and integer variables which are described in Table1 . Note that the range of the integer variable probes is changed for different verification instances, and since the abstract IP address 2 corresponds to a fresh address chosen by the concrete host we need only two buffers for the abstract hosts (corresponding to addresses of type 0 and 1).... ..."

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### Table 4. Mapping results for bit-serial multiplier over GF(2m) MUX-based FPLDs do not reach the capacity of LUT-based architectures. But ACT-3 FPGAs tend to be faster with increasing eld dimension m. Table3 also shows that the additional 3-input LUT in the XC4000 can be used e ectively to reduce the number of CLBs and/or the logic depth in comparison with the pure 4-input LUT structure of the FLEX8000 devices. On average, both device series exhibit the same utilization and speed. But in contrast to Altera apos;s FLEX8000 devices, unused registers of CLBs that implement combinatorial logic functions may still be used for other circuitry in a XC4000 device, e.g. for serial-

### Table 1. Formal verification using BAN logic.

"... In PAGE 9: ... The deduction is quite lengthy and we omit it. We only show the idealized protocol and stepwise results in Table1 and omit the detailed discussion of the process. Step 1 is trivial.... In PAGE 9: ... Since that member has the control over the generation of the Bloom filter, P believes the Bloom filter (Postulate (3)). Based on these postulates, we can mechanically deduct and get the results as shown in Table1 . Moreover, the logic forces us to explicitly write down our assumptions to clarify our design goals.... ..."

### Table 13: Comparison of GF(2m) ECPM hardware de- signs.

"... In PAGE 9: ... Table13 shows the parameters of previous hardware im- plementations of accelerators for EC scalar multiplica- tion. Due to different hardware configurations and differ- ent amount of functionality the numbers cannot be com- pared directly.... ..."