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181
Coil sensitivity encoding for fast MRI. In:
- Proceedings of the ISMRM 6th Annual Meeting,
, 1998
"... New theoretical and practical concepts are presented for considerably enhancing the performance of magnetic resonance imaging (MRI) by means of arrays of multiple receiver coils. Sensitivity encoding (SENSE) is based on the fact that receiver sensitivity generally has an encoding effect complementa ..."
Abstract
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Cited by 193 (3 self)
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complementary to Fourier preparation by linear field gradients. Thus, by using multiple receiver coils in parallel scan time in Fourier imaging can be considerably reduced. The problem of image reconstruction from sensitivity encoded data is formulated in a general fashion and solved for arbitrary coil
PARALLEL VIDEO DECODING IN THE EMERGING HEVC STANDARD
"... In this paper we propose and evaluate a parallelization strat-egy for the emerging HEVC video coding standard. The pro-posed strategy is based on entropy slices which allows ex-ploiting parallelism in the entropy decoding stage while main-taining high coding efficiency. Our approach requires to en-c ..."
Abstract
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Cited by 2 (0 self)
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In this paper we propose and evaluate a parallelization strat-egy for the emerging HEVC video coding standard. The pro-posed strategy is based on entropy slices which allows ex-ploiting parallelism in the entropy decoding stage while main-taining high coding efficiency. Our approach requires to en-code
Vsched: Mixing batch and interactive virtual machines using periodic real-time scheduling
- In Proceedings of ACM/IEEE SC 2005 (Supercomputing
, 2005
"... We are developing Virtuoso, a system for distributed computing using virtual machines (VMs). Virtuoso must be able to mix batch and interactive VMs on the same physical hardware, while satisfying constraints on responsiveness and compute rates for each workload. VSched is the component of Virtuoso t ..."
Abstract
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Cited by 72 (16 self)
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constraints to be straightforwardly described using a period and a slice within the period, and it allows for fast and simple admission control. This paper makes the case for periodic real-time scheduling for VM-based computing environments, and then describes and evaluates VSched. It also applies VSched
Mitosis Compiler: An Infrastructure for Speculative Threading Based on PreComputation Slices
- In Conference on Programming Language Design and Implementation
, 2005
"... Speculative parallelization can provide significant sources of additional thread-level parallelism, especially for irregular applications that are hard to parallelize by conventional approaches. In this paper, we present the Mitosis compiler, which partitions applications into speculative threads, w ..."
Abstract
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Cited by 81 (4 self)
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, with special emphasis on applications for which conventional parallelizing approaches fail. The management of inter-thread data dependences is crucial for the performance of the system. The Mitosis framework uses a pure software approach to predict/compute the thread’s input values. This software approach
SEMAC: Slice Encoding for Metal Artifact Correction
- in MRI, Mag. Res. Med
, 2009
"... Metallic implants, such as pedicle screws, are commonly used in orthopedic surgery to fixate fractures, replace arthritic joints, and to align and immobilize vertebra. In the United States alone, there were 325,000 spinal fusions performed in 2003 and 450,000 primary or revision total knee arthropl ..."
Abstract
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Cited by 3 (0 self)
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Metallic implants, such as pedicle screws, are commonly used in orthopedic surgery to fixate fractures, replace arthritic joints, and to align and immobilize vertebra. In the United States alone, there were 325,000 spinal fusions performed in 2003 and 450,000 primary or revision total knee
Abstract Probabilistic Advanced Reservations for Batch-scheduled Parallel Machines
"... In high-performance computing (HPC) settings, in which multiprocessor machines are shared among users with potentially competing resource demands, processors are allocated to user workload using space sharing. Typically, users interact with a given machine by submitting their jobs to a centralized b ..."
Abstract
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Cited by 1 (0 self)
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In high-performance computing (HPC) settings, in which multiprocessor machines are shared among users with potentially competing resource demands, processors are allocated to user workload using space sharing. Typically, users interact with a given machine by submitting their jobs to a centralized
VARQ: Implementing Probabilistic Advanced Reservations for Batch-scheduled Parallel Machines
"... In high-performance computing (HPC) settings, in which multiprocessor machines are shared among users with potentially competing resource demands, processors are allocated to user workload using space sharing. Typically, users interact with a given machine by submitting their jobs to a centralized b ..."
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In high-performance computing (HPC) settings, in which multiprocessor machines are shared among users with potentially competing resource demands, processors are allocated to user workload using space sharing. Typically, users interact with a given machine by submitting their jobs to a centralized
The Design and Evaluation of Hierarchical Multilevel Parallelisms for H.264 Encoder on Multi-core Architecture
"... Abstract. As a video coding standard, H.264 achieves high compress rate while keeping good fidelity. But it requires more intensive computation than before to get such high coding performance. A Hierarchical Multi-level Parallelisms (HMLP) framework for H.264 encoder is proposed which integrates fou ..."
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Cited by 1 (0 self)
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Abstract. As a video coding standard, H.264 achieves high compress rate while keeping good fidelity. But it requires more intensive computation than before to get such high coding performance. A Hierarchical Multi-level Parallelisms (HMLP) framework for H.264 encoder is proposed which integrates
Study of Thread Level Parallelism in a Video Encoding Application for Chip Multiprocessor Design
"... In media applications there is a high level of available thread level parallelism (TLP). In this paper we study the intra TLP in a video encoder. We show that a well-distributed highly optimized encoder running on a symmetric multiprocessor (SMP) system can run 3.2 faster on a 4-way SMP machine than ..."
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to evaluate the dataflow between processors for the video encoder running on an SMP system. An estimation of the dataflow is done with L2 cache miss event counters using Intel VTune performance analyzer. The experimental measurements are compared to theoretical results.
High Level Optimized Parallel Specification of a H.264/AVC Video Encoder
"... Abstract: H.264/AVC (Advanced Video Codec) is a new video coding standard developed by a joint effort of the ITU-TVCEG and ISO/IEC MPEG. This standard provides higher coding efficiency relative to former standards at the expense of higher computational requirements. Implementing the H.264 video enco ..."
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) model of computation and the YAPI programming C++ runtime library. To demonstrate the effectiveness of the obtained parallel model of the H.264 encoder, the encoding performances have been evaluated by system-level simulations targeting multiple multiprocessors platforms.
Results 1 - 10
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181