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Incremental Runtime-generation of Optimisation Problems using RAG-controlled Rewriting
"... Abstract-In the era of Internet of Things, software systems need to interact with many physical entities and cope with new requirements at runtime. Self-adaptive systems aim to tackle those challenges, often representing their context with a runtime model enabling better reasoning capabilities. How ..."
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computation overhead. We propose applying scalable, incremental change management of runtime models in the presence of a complex model to text transformation. In this paper, we present and evaluate an example of code generation of integer linear programs. In our case study using synthesized models, we saved
ASIC Implementation and Analysis of Extrinsic EHW Based Power and Area Optimised 8-Bit Asynchronous Parallel MAC
, 2009
"... In computing, especially in digital signal processing, multiply-accumulate is a common operation that computes the product of two numbers and adds that product to an accumulator. The VERILOG code for MAC operation is simulated and synthesized in Vendors tool like XILINX ISE and ALTERA QUARTUS II wit ..."
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In computing, especially in digital signal processing, multiply-accumulate is a common operation that computes the product of two numbers and adds that product to an accumulator. The VERILOG code for MAC operation is simulated and synthesized in Vendors tool like XILINX ISE and ALTERA QUARTUS II
Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis
, 2008
"... The paper introduces a new formal model for specifying control paths in the context of asynchronous system design. The model, called Conditional Partial Order Graph (CPOG), is capable of capturing concurrency and choice in a system's behaviour in a compact and e cient way. A problem of CPOG syn ..."
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Cited by 7 (6 self)
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synthesis is formulated and solved; various CPOG optimisation techniques are presented. The introduced model can be used for the specification of system behaviour and for synthesis of area-efficient dynamically reconfigurable controllers. The synthesis of a controller is based on a novel generic
Versatile High-level Synthesis of Self-checking Datapaths Using an On-line Testability Metric
"... There have been several recent attempts to include duplication-based on-line testability in behaviourally synthesized designs. In this paper, on-line testability is considered within the optimisation process of iterative, cost function-driven high-level synthesis, such that on-line testing resources ..."
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There have been several recent attempts to include duplication-based on-line testability in behaviourally synthesized designs. In this paper, on-line testability is considered within the optimisation process of iterative, cost function-driven high-level synthesis, such that on-line testing
