### Table 2 Logic family Average output

2001

"... In PAGE 5: ... A performance comparison of the TGL design style with the conventional CMOS, NMOS pass transistor and Domino CMOS logic style is carried out using an XOR structure. The simulated results are shown in Table2 , which reveals that the TGL style exhibits somewhat better power and delay performance than the CMOS style. The NMOS pass transistor style shows less power consumption than the TGL but they are not suitable for sea of gates design style as they leads to an wastage of prefabricated PMOS transistors.... In PAGE 25: ... The CORDIC arithmetic function. Table2 . Comparison of different logic families using the XOR structure.... ..."

Cited by 2

### Table 2: BAT Results with Manually Optimized Ordering

2002

"... In PAGE 9: ... After enough effort, we were able to find a good ordering that allows symbolic simulation to run. Table2 shows the results. In this sequence of experiments, we were able to complete the assertion check without using any constant logic values to simplify the assertion.... In PAGE 9: ... In this sequence of experiments, we were able to complete the assertion check without using any constant logic values to simplify the assertion. By comparing the results in Table 1 and in Table2 , we observe that variable ordering sig- nificantly impacts the performance of symbolic simulation. For the OBDD sizes, we show two types of data: the total number of OBDD nodes at the end of symbolic simulation (to- tal OBDD nodes), and the maximum number of OBDD nodes during the symbolic simulation (max OBDD nodes).... ..."

Cited by 1

### Table 13 - Representative Porosities for Optimization Cumulative Distribution

"... In PAGE 3: ...etween 34.5 and 37.5 percent. For each of these brackets, a representative value was selected, as listed in Table13 . For each of the representative values, the engineering parameters were optimized.... ..."

### Table 1: Percentage Reduction Factor of Cumulative Optimizations

"... In PAGE 15: ... The optimizations were implemented and tested in a layered approach in the order that they were discussed previously. Table1 shows the percentage reduction factor of the search space given the addition of each optimiza- tion. These data are identical for all four formula- tions B, O, P, and R.... ..."

### Table 2: Technology Mapping results

"... In PAGE 8: ... The results show that the Boolean approach reduces the number of matching algorithm calls, nd smaller area circuits in better CPU time, and reduces the initial network graph because generic 2-input base function are used. Table2 presents a comparison between SIS and Land for the library 44-2.genlib, which is distributed with the SIS package.... ..."

### Table 3b. Solution Statistics for Model 2 (Minimization)

1999

"... In PAGE 4: ...6 Table 2. Problem Statistics Model 1 Model 2 Pt Rows Cols 0/1 Vars Rows Cols 0/1 Vars 1 4398 4568 4568 4398 4568 170 2 4546 4738 4738 4546 4738 192 3 3030 3128 3128 3030 3128 98 4 2774 2921 2921 2774 2921 147 5 5732 5957 5957 5732 5957 225 6 5728 5978 5978 5728 5978 250 7 2538 2658 2658 2538 2658 120 8 3506 3695 3695 3506 3695 189 9 2616 2777 2777 2616 2777 161 10 1680 1758 1758 1680 1758 78 11 5628 5848 5848 5628 5848 220 12 3484 3644 3644 3484 3644 160 13 3700 3833 3833 3700 3833 133 14 4220 4436 4436 4220 4436 216 15 2234 2330 2330 2234 2330 96 16 3823 3949 3949 3823 3949 126 17 4222 4362 4362 4222 4362 140 18 2612 2747 2747 2612 2747 135 19 2400 2484 2484 2400 2484 84 20 2298 2406 2406 2298 2406 108 Table3 a. Solution Statistics for Model 1 (Maximization) Pt Initial First Heuristic Best Best LP Obj.... In PAGE 5: ...) list the elapsed time when the heuristic procedure is first called and the objective value corresponding to the feasible integer solution returned by the heuristic. For Table3 a, the columns Best LP Obj. and Best IP Obj.... In PAGE 5: ... report, respectively, the LP objective bound corresponding to the best node in the remaining branch-and-bound tree and the incumbent objective value corresponding to the best integer feasible solution upon termination of the solution process (10,000 CPU seconds). In Table3 b, the columns Optimal IP Obj., bb nodes, and Elapsed Time report, respectively, the optimal IP objective value, the total number of branch-and-bound tree nodes solved, and the total elapsed time for the solution process.... ..."

### Table 1: Predictions of our Theory

"... In PAGE 17: ... In other words, our model predicts a political business cycle in in#0Dation but not in employment. Our theory also predicts that the variances of in#0Dation and employment are unre- lated to the status of the central bank; see Table1 for the analytical details. As regards the variance of employment this is consistent with the cumulative empirical evidence; see e.... ..."

### Table 2: Software Engineering Educational Approaches and the Learning Theories they Leverage.

2005

"... In PAGE 22: ... For instance, Method A might be optimal with x theories, but once it tries to incorporate (x + 1) theories, the effectiveness may start to decrease. In Table2 , the analysis that is based on this assumption is presented. Table 2 is a ma- trix of software engineering educational approaches, and the learning theories that they leverage.... In PAGE 28: ...6 Projects Plus Realism (All Others) The rest of the Projects plus Realism approaches presented in Section 2.1 leverage the same set of learning theories, therefore they are all placed at the end of Table2 . Because the goal of a project in general is to teach students how to perform tasks using the knowl- edge they are taught, all approaches that involve a project are essentially Learning by Do- ing approaches.... In PAGE 31: ... This makes logical sense: If we want to better prepare students for the real world, it is only common sense that we try to introduce the real world to them sooner rather than later. However, if we look again at Table2 , we can see that the majority of these approaches only employ two learning theories: Learning by Doing and Situated Learning. Table 3: Frequency and Breakdown of Each Software Engineering Educational Approach.... ..."

### Table 1: Area/throughput design results of stochastic ray tracing formfactor calculations on Xilinx Virtex family FPGAs.

"... In PAGE 2: ... Appropriate throughput/area arithmetic cores are then automatically instantiated for arithmetic op- erations from a device-independent arithmetic library written in Handel-C, or a database of device-specific cores pregenerated using Xilinx Coregen. Table1 demonstrates how the design pattern is used to automatically scale performance for different size FPGAs in the Xilinx Virtex series. For each de- vice, the entire throughput/area design space is de- termined by exhaustive compilation.... ..."