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38
On the Complexity of Robust Source-to-Source Translation from CUDA to OpenCL
, 2013
"... The use of hardware accelerators in high-performance computing has grown increasingly prevalent, particularly due to the growth of graphics processing units (GPUs) as general-purpose (GPGPU) accelerators. Much of this growth has been driven by NVIDIA’s CUDA ecosystem for developing GPGPU application ..."
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(accelerated processing unit), FPGA (field programmable gate array), and DSP (digital signal processor). The above, coupled with the broader array of devices supporting OpenCL and the significant conceptual and syntactic overlap between CUDA and OpenCL, motivated the creation of a CUDA-to-OpenCL source
NEON implementation of an attribute-based encryption scheme
"... Abstract. In 2011, Waters presented a ciphertext-policy attribute-based encryption protocol that uses bilinear pairings to provide control access mechanisms, where the set of user’s attributes is specified by means of a linear secret sharing scheme. Some of the applications foreseen for this protoco ..."
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Cited by 6 (1 self)
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for this protocol lie in the context of mobile devices such a smartphones and tablets, which in a majority of instances are powered by an ARM processor supporting the NEON vector set of instructions. In this paper we present the design of a software cryptographic library that implements a 127-bit security level
FourQNEON: Faster Elliptic Curve Scalar Multiplications on ARM Processors
"... Abstract. We present a high-speed, high-security implementation of the recently proposed elliptic curve FourQ (ASIACRYPT 2015) for 32-bit ARM processors with NEON support. Exploiting the versatile and compact arithmetic of this curve, we design a vectorized implementation that achieves high-perform ..."
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Abstract. We present a high-speed, high-security implementation of the recently proposed elliptic curve FourQ (ASIACRYPT 2015) for 32-bit ARM processors with NEON support. Exploiting the versatile and compact arithmetic of this curve, we design a vectorized implementation that achieves high
7 A Scalable Software Framework for Stateful Stream Data Processing on Multiple GPUs and Applications
"... Abstract During the past few years the increase of computational power has been realized using more processors with multiple cores and specific processing units like Graphics Processing Units (GPUs). Also, the introduction of program-ming languages such as CUDA and OpenCL makes it easy, even for non ..."
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for non-graphics programmers, to exploit the computational power of massively parallel processors available in current GPUs. Although CUDA and OpenCL relieve programmers from considering many low-level details of parallel programming on multiple cores on a single GPU, the same support at a higher level
Optimizing OpenCLTM on CPUs
"... • OpenCL is a Platform API which supports a uniform programming environment across devices – Enables heterogeneous parallel computations – Unique in its ability to coordinate CPUs, GPUs, etc • The goal of using OpenCL should be to make the best use of all the available resources (CPU’s, GPU’s) from ..."
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Cited by 1 (0 self)
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• OpenCL is a Platform API which supports a uniform programming environment across devices – Enables heterogeneous parallel computations – Unique in its ability to coordinate CPUs, GPUs, etc • The goal of using OpenCL should be to make the best use of all the available resources (CPU’s, GPU’s) from
D3D9 Media Surface Sharing Between Intel ® Quick Sync Video and
"... Intel has defined an extension to OpenCL * v1.0 and later, allowing applications to directly access images embedded in Microsoft DirectX * 9 (DX9) media surfaces, without first copying them. For OpenCL v1.2, the Khronos standards organization has defined a standardized extension for the same purpose ..."
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enhancement during playback, video editing with effects, and video generation and encoding OpenCL and Intel QSV Media Surface Sharing Intel QSV supports video decode and encode acceleration by Intel ® processor graphics and can be accessed by applications using the Intel ® Media SDK. 1 OpenCL 2 is a framework
Microkernel Hypervisor for a Hybrid ARM-FPGA Platform
"... Abstract—Reconfigurable architectures have found use in a wide range of application domains, but mostly as static ac-celerators for computationally intensive functions. Commodity computing adoption has not taken off due primarily to design complexity challenges. Yet reconfigurable architectures offe ..."
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execution and management of soft-ware and hardware tasks using a microkernel-based hypervisor running on a commercial hybrid computing platform (the Xilinx Zynq). We demonstrate a framework based on the CODEZERO hypervisor, which has been modified to leverage the capabilities of the FPGA fabric. It supports
978-1-4799-5944-0/14/$31.00 c©2014 IEEE A Unified OpenCL-flavor Programming Model with Scalable Hybrid Hardware Platform on FPGAs
"... Abstract—Hardware accelerators are capable of achieving sig-nificant performance improvement. However, designing hardware accelerators lacks the flexibility and the productivity. Combining hardware accelerators with multiprocessor system-on-chip (MP-SoC) is an alternative way to balance the flexibil ..."
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the flexibility, the produc-tivity, and the performance. In this work, we present a unified hybrid OpenCL-flavor (HOpenCL) parallel programming model on MPSoC supporting both hardware and software kernels. By integrating the HOpenCL hardware IPs and software libraries, the same kernel function can execute
Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators
- Proc. Int’l Conf. Hardware/Software Codesign and System Synthesis (CODES/ISSS 07), ACM Press, 2007
"... We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circuits on FPGAs (field-programmable gate arrays). Building on dynamic synthesis for single-processor single-thread systems, ..."
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Cited by 6 (1 self)
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architectural simulation framework we developed, showing application speedups of 4x to 502x, averaging 130x compared to a multiprocessor system having four ARM11 microprocessors, for eight benchmark applications. Even compared to a 64-processor system, thread warping achieves 11x speedup.
Software Defined Radio Implemented using the OSSIE Core Framework Deployed on a
- Virginia Polytechnic Institute and State University, USA. December
"... Software Defined Radios are computer based systems that emulate the behavior of tradi-tional radio systems by processing digitized radio signals. A SDR replaces the traditional fixed hardware radio with a system that may be reconfigured, both during operation to pro-vide greater flexibility and by p ..."
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Cited by 3 (0 self)
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. OSSIE, an open source SCA implementation developed at Virginia Tech, was ported to the ARM processor by adding support for building OSSIE into the OpenEmbedded build system. Once the port for the OMAP starter kit was complete, it became possible to easily re-target OSSIE for a
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