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678,952
Route Packets, Not Wires: On-Chip Interconnection Networks
, 2001
"... Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structur ..."
Abstract
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Cited by 864 (10 self)
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the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks. 1
Wattch: A Framework for Architectural-Level Power Analysis and Optimizations
- In Proceedings of the 27th Annual International Symposium on Computer Architecture
, 2000
"... Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high ..."
Abstract
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Cited by 1295 (43 self)
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Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve
Foundations for the Study of Software Architecture
- ACM SIGSOFT SOFTWARE ENGINEERING NOTES
, 1992
"... The purpose of this paper is to build the foundation for software architecture. We first develop an intuition for software architecture by appealing to several well-established architectural disciplines. On the basis of this intuition, we present a model of software architec-ture that consists of th ..."
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Cited by 784 (35 self)
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The purpose of this paper is to build the foundation for software architecture. We first develop an intuition for software architecture by appealing to several well-established architectural disciplines. On the basis of this intuition, we present a model of software architec-ture that consists
Simultaneous Multithreading: Maximizing On-Chip Parallelism
, 1995
"... This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar’s multiple functional units in a single cycle. We present several models of simultaneous multithreading and compare them with alternative organizations: a wide s ..."
Abstract
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Cited by 802 (48 self)
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superscalar, a fine-grain multithreaded processor, and single-chip, multiple-issue multiprocessing architectures. Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor. Simultaneous
Towards an Active Network Architecture
- Computer Communication Review
, 1996
"... Active networks allow their users to inject customized programs into the nodes of the network. An extreme case, in which we are most interested, replaces packets with "capsules" -- program fragments that are executed at each network router/switch they traverse. Active architectures permit ..."
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Cited by 492 (7 self)
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Active networks allow their users to inject customized programs into the nodes of the network. An extreme case, in which we are most interested, replaces packets with "capsules" -- program fragments that are executed at each network router/switch they traverse. Active architectures permit
A Network-on-Chip Architecture
"... The growing complexity of embedded multi-processor architectures for digi-tal media processing will soon require highly scalable communication infra-structures. Packet switched Net-works-on-Chip (NoC) have been proposed to support the trend for Systems-on-Chip integration. In this paper, an advanced ..."
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, an advanced NoC architecture, called Xpipes, targeting high perform-ance and reliable communication for on-chip multi-processors is intro-duced. It consists of a library of soft macros (switches, network interfaces and links) that are design-time com-posable and tunable so that domain-specific heterogeneous
An Energy and Performance Exploration of Network-on-Chip Architectures
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol 17, Issue
, 2009
"... Abstract—In this paper, we explore the designs of a cir-cuit-switched router, a wormhole router, a quality-of-service (QoS) supporting virtual channel router and a speculative virtual channel router and accurately evaluate the energy-performance tradeoffs they offer. Power results from the designs p ..."
Abstract
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Cited by 8 (2 self)
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met-rics are also presented to allow a comparison of implementation costs. Index Terms—Circuit-switching networks, evaluation, low-power design, measurement, network-on-chip (NoC), packet-switching networks, performance comparison, simula-tion. I.
Mediators in the architecture of future information systems
- IEEE COMPUTER
, 1992
"... The installation of high-speed networks using optical fiber and high bandwidth messsage forwarding gateways is changing the physical capabilities of information systems. These capabilities must be complemented with corresponding software systems advances to obtain a real benefit. Without smart softw ..."
Abstract
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Cited by 1128 (20 self)
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The installation of high-speed networks using optical fiber and high bandwidth messsage forwarding gateways is changing the physical capabilities of information systems. These capabilities must be complemented with corresponding software systems advances to obtain a real benefit. Without smart
A formal basis for architectural connection
- ACM TRANSACTIONS ON SOJIWARE ENGINEERING AND METHODOLOGY
, 1997
"... ..."
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