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208
Computing with nanoscale memory: model and architecture
, 2009
"... Abstract—Emerging nanoscale devices hold tremendous po-tential in terms of integration density, low power operation and switching speed. Unlike CMOS devices, however, majority of these devices are not suitable for implementing cascaded, irregular logic structure. On the other hand, dense and periodi ..."
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Cited by 4 (3 self)
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and periodic structures of most emerging nanodevices as well as their bi-stable nature make them amenable to large high-density memory array design. Moreover, self-assembly of many nanostructures is effi-cient for a bottom-up system design flow. Hence, reconfigurable computing paradigms that use memory
Design and Performance Analysis of Nanoscale Content- Addressable Memories
"... Abstract — This paper proposes a nanoscale content addressable memory (CAM) architecture. The type of CAM considered is adept at handling the irregular patterning of nanoscale components but requires an encoding scheme to be useful. We show how a randomly configured interface between the micro and ..."
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Abstract — This paper proposes a nanoscale content addressable memory (CAM) architecture. The type of CAM considered is adept at handling the irregular patterning of nanoscale components but requires an encoding scheme to be useful. We show how a randomly configured interface between the micro
Global Multiple-Valued Clock Approach for High- Performance Multi-Phase Clock Integrated Circuits
"... Abstract – Some high performance digital integrated circuits use multi-phase clock distribution systems with level-sensitive latches as clocked storage elements. A set of N periodic non-overlapping binary clock signals propagate over each of the clock phase distribution networks and drive disjoint s ..."
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Cited by 2 (1 self)
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single global clock distribution network for a multi-valued (MV) clock signal in combination with level-sensitive latches designed to be transparent for a specific portion of the global MV clock signal. This approach is compatible with conventional binary logic since the only non-binary components
Fault-Tolerant Multi-Level Logic Decoder for Nanoscale Crossbar Memory Arrays ∗
"... Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using multiple threshold voltages (VT), which is ena ..."
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Cited by 2 (1 self)
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Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using multiple threshold voltages (VT), which
Analysis of Power Dissipation in DRAM Cells Design for Nanoscale Memories
- International Journal of Information Technology and Knowledge Management
, 2009
"... In this paper power dissipation analysis for DRAM design have been carried out for the Nanoscale memories. Many advanced processors now have on chip instructions and data memory using DRAMs. The major contribution of power dissipation in DRAM is off-state leakage current. Thus, improving the power ..."
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Cited by 1 (0 self)
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In this paper power dissipation analysis for DRAM design have been carried out for the Nanoscale memories. Many advanced processors now have on chip instructions and data memory using DRAMs. The major contribution of power dissipation in DRAM is off-state leakage current. Thus, improving the power
Foundations for engineering biology.
- Nature
, 2005
"... Engineered biological systems have been used to manipulate information, construct materials, process chemicals, produce energy, provide food, and help maintain or enhance human health and our environment. Unfortunately, our ability to quickly and reliably engineer biological systems that behave as ..."
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Cited by 132 (2 self)
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be used to evolve biological systems to perform these tasks… Time's up! The abovementioned applications of synthetic biology could find uses in the construction of templated surfaces for nanoscale materials fabrication, the characterization of physical performance limits for eukaryotic gene
Design Considerations/Insights for Memristor-Based Memory Arrays
"... Abstract—To achieve high data density with low power con-sumption, technology migration into nano and molecular scales have been proposed. Discovery of the memristor has enabled the realization of denser nano-scale logic and memory systems. This is due to the memristor distinctive characteristics su ..."
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such as storing the historic state of the current passing through it, nano-scale device, and low power consumption. This work describes the design considerations of using a memristor in realization of a memory cell. Based on this analysis, a new read/write circuit is proposed and verified using a simulation tool
Materials for an exploratory theory of the network society.
- The British Journal of Sociology
, 2000
"... ABSTRACT This article aims at proposing some elements for a grounded theor y of the network society. The network society is the social structure characteristic of the Information Age, as tentatively identi ed by empirical, cross-cultural investigation. It permeates most societies in the world, in v ..."
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Cited by 122 (0 self)
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to perform a useful function it is phased out from the network, and the network rearranges itself -as cells do in biological processes. Some nodes are more important than others, but they all need each other as long as they are within the network. And no nodal domination is systemic. Nodes increase
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
- IEEE Transactions on Dependable and Secure Computing, 1(2):128–143, April-June
"... Abstract—Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in highperformance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rat ..."
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Cited by 88 (1 self)
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Abstract—Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in highperformance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error
DESIGN INCLUDES A SIMPLE ACCUMULATOR-BASED INSTRUCTION-SET ARCHITECTURE, SENSORS, LIMITED MEMORY, AND INSTRUCTION-FUSED SENSING. USING NSP TECHNOLOGY BASED ON OPTICAL RESONANCE ENERGY TRANSFER LOGIC HELPS THEM DECREASE THE DESIGN’S SIZE; THEIR SMALLEST DE
"... phenomena is a critical component of many scientific disciplines. The ability to retrieve nanoscale information from within macroscale systems is particularly useful in biological fields, where the diversity of molecular components and interaction dynamics within a cell make it difficult to monitor ..."
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phenomena is a critical component of many scientific disciplines. The ability to retrieve nanoscale information from within macroscale systems is particularly useful in biological fields, where the diversity of molecular components and interaction dynamics within a cell make it difficult to monitor
Results 1 - 10
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208
