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MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP
"... Severalresearchershaverecognizedinrecentyearsthattoday’s workloads require a microarchitecture that can handle singlethreadedcodeathighperformance,andmulti-threadedcodeathigh throughput,whileconsumingnomoreenergythanisnecessary.This paperproposesMorphCore,auniqueapproachtosatisfyingthese competingre ..."
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Severalresearchershaverecognizedinrecentyearsthattoday’s workloads require a microarchitecture that can handle singlethreadedcodeathighperformance,andmulti-threadedcodeathigh throughput,whileconsumingnomoreenergythanisnecessary.This paperproposesMorphCore
Revisiting ILP Designs for Throughput-Oriented GPGPU Architecture
"... Abstract—Many-core architectures such as graphics processing units (GPUs) rely on thread-level parallelism (TLP) to overcome pipeline hazards. Consequently, each core in a many-core processor employs a relatively simple in-order pipeline with limited capability to exploit instruction-level paralleli ..."
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for high TLP and those customized with ILP techniques. Our results show that our heterogeneous GPU architecture achieves high throughput as well as high energy-and area-efficiency compared to homogenous designs.
J.L.: Resource sharing control in simultaneous multithreading microarchitectures
- In: ACSAC ’08: Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference. (2008) 1–8
"... Simultaneous MultiThreading (SMT) achieves improved system resource utilization and accordingly higher instruction throughput because it exploits Thread-Level Parallelism (TLP) in addition to conventional Instruction-Level Parallelism (ILP). The key to high-performance SMT is to optimize the distrib ..."
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Cited by 1 (1 self)
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Simultaneous MultiThreading (SMT) achieves improved system resource utilization and accordingly higher instruction throughput because it exploits Thread-Level Parallelism (TLP) in addition to conventional Instruction-Level Parallelism (ILP). The key to high-performance SMT is to optimize
A Flexible Heterogeneous Multi-Core Architecture
"... Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this environment are nonuniform. Thus, multi-core processors should be flexible enough ..."
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Cited by 23 (0 self)
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this processor is able to outperform previous state-of-the-art high-performance processor research by 12 % on SpecFP. We show how in a quadthreaded/quad-core environment the processor outperforms a statically allocated configuration in both throughput and 1 harmonic mean, two commonly used metrics to evaluate
