Wire routing is an important component in the design of very large scale integrated circuits (VLSI). In a recent work Erdem et al. argued that routing problems can be solved by general-purpose answer-set programming solvers. They proposed to view routing as a planning problem in which multiple

apart from existing cellular systems and in fact makes its design much more challenging. In this environment, we investigate routing strategies that scale well to large populations and can handle mobility. In addition, we address the need to support multimedia communications, with low latency

Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router

-based multicast protocols, recently (re-)discovered in wired networks, appear to be a viable means to “fight fire with fire ” by exploiting the nondeterministic nature of ad hoc networks. This paper presents a protocol that is designed to meet a more practical specification of probabilistic reliability

The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently de-veloped FPGAs (e.g., Virtex-II), there are more versatile wire types and richer connections between them than those

the interconnect, be it a conventional bus-based or a network-on-chip, remain susceptible to attacks as they usually employ long wires in the upper metal layers. In this study we propose a method of improving chip-level security by using multipath routing in networks-on-chip. The technique consists of splitting a

Routing (AWR) algorithm based on evolutionary princi-ples. In the proposed algorithm (dubbed EWRA, where "E " stands for evolutionary), populations of wiring net-works evolve through the action of stochastic operators conceived from the heuristics of manual wire-routing. In each

Abstract. Routing wires are dominant performance stoppers in deep sub-micron technologies, and there is an urgent need to take them into account already at higher levels of abstraction. However, the normal design flow gives the designer only limited control over the details of the lower levels

, integrates bidirectional verification to defend against rushing attacks, accommodates multipath routing to multiple base stations, enables secure joining/leaving, and incorporates a novel pairwise key setup scheme based on transitory global keys that is more resilient than LEAP. Simulation results

must cross more chip boundaries. Current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). These logical wires are not active simultaneouslyand are only switched at emulation clock speeds