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More on Wire Routing with ASP
- in Working Notes of the AAAI Spring Symposium on Answer Set Programming
, 2001
"... Wire routing is an important component in the design of very large scale integrated circuits (VLSI). In a recent work Erdem et al. argued that routing problems can be solved by general-purpose answer-set programming solvers. They proposed to view routing as a planning problem in which multiple ..."
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Cited by 4 (0 self)
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Wire routing is an important component in the design of very large scale integrated circuits (VLSI). In a recent work Erdem et al. argued that routing problems can be solved by general-purpose answer-set programming solvers. They proposed to view routing as a planning problem in which multiple
Scalable routing strategies for ad hoc wireless networks
- IEEE JSAC
, 1999
"... In this paper, we consider a large population of mobile stations that are interconnected by a multihop wireless network. The applications of this wireless infrastructure range from ad hoc networking (e.g., collaborative, distributed computing) to disaster recovery (e.g., fire, flood, earthquake), l ..."
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Cited by 261 (15 self)
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apart from existing cellular systems and in fact makes its design much more challenging. In this environment, we investigate routing strategies that scale well to large populations and can handle mobility. In addition, we address the need to support multimedia communications, with low latency
PathFinder: A Negotiation-based Performancedriven Router for FPGAs”, FPGA
, 1995
"... Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router t ..."
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Cited by 204 (12 self)
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Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router
Route driven gossip: Probabilistic reliable multicast in ad hoc networks
- IN PROC. OF INFOCOM
, 2003
"... Traditionally, reliable multicast protocols are deterministic in nature. It is precisely this determinism that tends to become their limiting factor when aiming at reliability and scalability, particularly in highly dynamic networks, e.g., ad hoc networks. As probabilistic protocols, gossip-based ..."
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Cited by 128 (3 self)
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-based multicast protocols, recently (re-)discovered in wired networks, appear to be a viable means to “fight fire with fire ” by exploiting the nondeterministic nature of ad hoc networks. This paper presents a protocol that is designed to meet a more practical specification of probabilistic reliability
Wire type assignment for fpga routing
- In Proceedings of the International Symposium on Field Programmable Gate Arrays. 61–67
, 2003
"... The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently de-veloped FPGAs (e.g., Virtex-II), there are more versatile wire types and richer connections between them than those of the ..."
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Cited by 3 (1 self)
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The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently de-veloped FPGAs (e.g., Virtex-II), there are more versatile wire types and richer connections between them than those
routing
"... In a highly competitive consumer electronics industry, companies try to protect their IP and that of their customers from reverse-engineering attempts and sometimes they attempt to crate barriers against unauthorized use of their products in applications like Digital Rights Management or DRM. This t ..."
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the interconnect, be it a conventional bus-based or a network-on-chip, remain susceptible to attacks as they usually employ long wires in the upper metal layers. In this study we propose a method of improving chip-level security by using multipath routing in networks-on-chip. The technique consists of splitting a
An evolutionary method for automatic wire routing
- In Proceedings of the 20th International Conference on Industrial Electronics, Control and Instrumentation (IECON'94
, 1994
"... Routing (AWR) algorithm based on evolutionary princi-ples. In the proposed algorithm (dubbed EWRA, where "E " stands for evolutionary), populations of wiring net-works evolve through the action of stochastic operators conceived from the heuristics of manual wire-routing. In each wi ..."
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Cited by 1 (0 self)
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Routing (AWR) algorithm based on evolutionary princi-ples. In the proposed algorithm (dubbed EWRA, where "E " stands for evolutionary), populations of wiring net-works evolve through the action of stochastic operators conceived from the heuristics of manual wire-routing. In each
Wired: Wire-aware circuit design
- In Proc. of Conference on Correct Hardware Design and Verification Methods (CHARME
, 2005
"... Abstract. Routing wires are dominant performance stoppers in deep sub-micron technologies, and there is an urgent need to take them into account already at higher levels of abstraction. However, the normal design flow gives the designer only limited control over the details of the lower levels, risk ..."
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Cited by 22 (2 self)
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Abstract. Routing wires are dominant performance stoppers in deep sub-micron technologies, and there is an urgent need to take them into account already at higher levels of abstraction. However, the normal design flow gives the designer only limited control over the details of the lower levels
INSENS: Intrusion-tolerant routing in wireless sensor networks”, In:
, 2002
"... Abstract: This paper describes an INtrusion-tolerant routing protocol for wireless SEnsor NetworkS (INSENS). INSENS securely and efficiently constructs tree-structured routing for wireless sensor networks (WSNs). The key objective of an INSENS network is to tolerate damage caused by an intruder who ..."
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Cited by 107 (5 self)
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, integrates bidirectional verification to defend against rushing attacks, accommodates multipath routing to multiple base stations, enables secure joining/leaving, and incorporates a novel pairwise key setup scheme based on transitory global keys that is more resilient than LEAP. Simulation results
Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators
"... Existing FPGA-based logic emulators suffer from limited inter-chip communication bandwidth, resulting in low gate utilization (10 to 20 percent). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals mus ..."
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Cited by 85 (12 self)
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must cross more chip boundaries. Current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). These logical wires are not active simultaneouslyand are only switched at emulation clock speeds
Results 1 - 10
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