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Token flow control

by Amit Kumar, et al.
"... As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scalability and increasing bandwidth demands, state-of-the-art on-chip networks use a modular packet-switched design with route ..."
Abstract - Cited by 635 (35 self) - Add to MetaCart
synthetic traffic and traces from the SPLASH-2 benchmark suite show reduction in packet latency by up to 77.1 % with upto 39.6 % reduction in average router energy consumption as compared to a state-of-theart baseline packet-switched design. For the same saturation throughput as the baseline network, TFC

Design of Area Efficient Low Latency Sorting Units

by unknown authors
"... Abstract- Sorting is an important technique used in many applications such as visual processing unit (VPU), Digital Signal Processing (DSP), network processing etc. To achieve high throughput rates today's computers perform several operations simultaneously. This paper presents the efficient te ..."
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Abstract- Sorting is an important technique used in many applications such as visual processing unit (VPU), Digital Signal Processing (DSP), network processing etc. To achieve high throughput rates today's computers perform several operations simultaneously. This paper presents the efficient

Multiple-banked register file architectures

by José-Lorenzo Cruz , Antonio González , Mateo Valero , Nigel P Topham - In International Symposium on Computer Architecture(ISCA-27 , 2000
"... Abstract The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor generations, as they are expected to increase the issue width (which implies more register ports) and the size of the ..."
Abstract - Cited by 146 (12 self) - Add to MetaCart
provides low latency and simple bypass logic. We propose several caching policies and prefetching strategies and demonstrate the potential of this multiple-banked organization. For instance, we show that a two-level organization degrades IPC by 10% and 2% with respect to a non-pipelined single

A Modular Network Interface Design and Synthesis Outlook

by Brahim Attia, Abdelkirm Zitouni, Wissem Chouchenne, Kholdoun Torki, Rached Tourki
"... In recent years, as System on Chip design research is actively conducted, a large number of IPs is included in a system based on a Network on Chip (NoC). Different interfaces ’ specification of IP cores and different flow controls are used by router. They raise a considerable difficulty for adopting ..."
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for adopting NoC techniques. To facilitate the use of the NoC techniques an efficient design of the network interface (NI) unit that connects the switched network to the IP cores is required. In this paper, we present a new NI architecture for NoC with low latency and jitter constraints. We introduce a new

Indicators for Social and Economic Coping Capacity - Moving Toward a Working Definition of Adaptive Capacity”, Wesleyan-CMU Working Paper.

by Gary Yohe , Richard S J Tol , Gary Yohe , 2001
"... Abstract This paper offers a practically motivated method for evaluating systems' abilities to handle external stress. The method is designed to assess the potential contributions of various adaptation options to improving systems' coping capacities by focusing attention directly on the u ..."
Abstract - Cited by 109 (14 self) - Add to MetaCart
on the low side by 0 and on the high side by 5 according to systematic consideration of the degree to which each determinant would help or impede its adoption. Let these factors be denoted by ff j (k) for determinants k = 2, …, 8. We will argue that an overall feasibility factor for adaptation (j) should

A Modular Simulation Framework for Architectural Exploration of On-Chip Interconnection Networks

by Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens - In CODES+ISSS , 2003
"... Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prevent time consuming design changes late in the design flow, we propose the early exploration of the on-chip communication a ..."
Abstract - Cited by 21 (5 self) - Add to MetaCart
parameters like utilization, latency and throughput drives the mapping of the inter-module traffic to an efficient communication architecture. The effectiveness of our approach is demonstrated by the exemplary design of a high performance Network Processing Unit (NPU), which is compared against a commercial

Tolerance Band Modulation Methods for Modular Multilevel Converters

by Arman Hassanpoor , Kalle Ilves , Staffan Norrga , Lennart Ängquist , Hans-Peter Nee
"... Abstract Modular multilevel converters (M2C) are increasingly used in the high voltage direct current (HVDC) systems. The efficiency of M2C is highly related to the modulation technique which determines the switching frequency and capacitor voltage ripple in the converter station. A new approach to ..."
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Abstract Modular multilevel converters (M2C) are increasingly used in the high voltage direct current (HVDC) systems. The efficiency of M2C is highly related to the modulation technique which determines the switching frequency and capacitor voltage ripple in the converter station. A new approach

Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array

by Aaron Stillmaker, Lucas Stillmaker, Bevan Baas
"... Abstract—Data centers require significant and growing amounts of power to operate, and with increasing numbers of data centers worldwide, power consumption for enterprise workloads is a significant concern. Sorting is a key computational kernel in large database systems, and the development of energ ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
of energy efficient sorting capabilities would therefore significantly reduce data center power usage. We propose highly parallel sorting algorithms and mappings using a modular design for a fine-grained many-core system that greatly decreases the amount of energy consumed to perform sorts of arbitrarily

A Memory-Efficient and Modular Approach for String Matching on FPGAs

by Hoang Le, Viktor K. Prasanna
"... string matching demands exceptionally high performance to match the content of network traffic against a predefined database of malicious patterns. Much work has been done in this field; however, they result in low memory efficiency 1. Due to the available on-chip memory and the number of I/O pins o ..."
Abstract - Cited by 2 (0 self) - Add to MetaCart
of Field Programmable Gate Arrays (FPGAs), state-ofthe-art designs cannot support large dictionaries without using high-latency external DRAM. We propose a novel Memory efficient Architecture for large-scale String Matching (MASM), based on pipelined binary search tree. With memory efficiency close to 1

A Model Of Spatial Sorting In Animal Groups, With An Application To Honeybee Swarm Movement

by A. Merri Eld, M. R. Myerscough, N. Weber
"... A self-organising model of group formation (in three dimensional space) based on simple rules of avoidance, attraction and alignment is used to examine the spatial dynamics of animal groups. We discuss the dierent types of behaviour resulting from this model due to changes in these rules. In particu ..."
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A self-organising model of group formation (in three dimensional space) based on simple rules of avoidance, attraction and alignment is used to examine the spatial dynamics of animal groups. We discuss the dierent types of behaviour resulting from this model due to changes in these rules. In particular, the phenomenon of honeybee swarms migrating to a new nesting site is examined. The vast majority of the migrating swarm is uninformed as to the particular location of their new home. A small number of bees (in the swarm) have prior knowledge of the new location and guide the rest of the swarm to the new site. The model investigates a hypothesis of how this guidance procedure occurs. We conclude from the results of the model that one possible way for this process to occur is for the knowledgeable bees to guide the other members of the swarm with spatial cues. Key words: Self-organisation, spherical probability distribution, swarming behaviour, randomisation tests, Apis mellifera. 1
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