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170
Datapath Merging and Interconnection Sharing for Reconfigurable Architectures
, 2002
"... Recent work in reconfigurable computing research has shown that a substantial performance speedup can be achieved through architectures that map the most relevant application inner-loops to a reconfigurable datapath. Any solution to this problem must be able to synthesize a datapath for each loop an ..."
Abstract
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Cited by 11 (3 self)
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Recent work in reconfigurable computing research has shown that a substantial performance speedup can be achieved through architectures that map the most relevant application inner-loops to a reconfigurable datapath. Any solution to this problem must be able to synthesize a datapath for each loop
Merging for Reconfigurable Architectures
, 2003
"... Recon gurable systems have been proved to achieve signi cant performance speedup through architectures that map the most time-consuming application kernel modules or inner-loops to a recon gurable datapath. As each portion of the application starts to execute, the system recon gures the datap ..."
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be reused across the application as much as possible. We represent each piece of the application as a control/data-ow graph (CDFG) and merge them together, synthesizing a single recon gurable datapath. The CDFG merging process enables the reuse of hardware blocks and interconnections by identifying
Efficient datapath merging for partially reconfigurable architectures
- in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
, 2005
"... Abstract—Reconfigurable systems have been shown to achieve significant performance speedup through architectures that map the most time-consuming application kernel modules or inner loops to a reconfigurable datapath. As each portion of the application starts to execute, the system partially reconfi ..."
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Cited by 22 (0 self)
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hardware blocks and interconnections. In this paper we present a novel technique for the DFG merge problem, and we evaluate it using programs from the MediaBench benchmark. Our algorithm execution time approaches the fastest previous solution to this problem and produces datapaths with an average area
The Motivation, Architecture and Demonstration of Ultralight Network Testbed
"... In this paper we describe progress in the NSF-funded Ultralight project and a recent demonstration of Ultralight technologies at SuperComputing 2005 (SC|05). The goal of the Ultralight project is to help meet the data-intensive computing challenges of the next generation of particle physics experime ..."
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Cited by 2 (1 self)
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early results in the various working areas of the project. The remainder of the paper describes our experiences of the Ultralight network architecture, kernel setup, application tuning and configuration used during the bandwidth challenge event at SC|05. During this Challenge, we achieved a record
Cobot architecture
- IEEE Transactions on Robotics and Automation
, 2001
"... Abstract—We describe a new robot architecture: the collabo-rative robot, or cobot. Cobots are intended for direct physical in-teraction with a human operator. The cobot can create smooth, strong virtual surfaces and other haptic effects within a shared human/cobot workspace. The kinematic properties ..."
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Cited by 52 (14 self)
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Abstract—We describe a new robot architecture: the collabo-rative robot, or cobot. Cobots are intended for direct physical in-teraction with a human operator. The cobot can create smooth, strong virtual surfaces and other haptic effects within a shared human/cobot workspace. The kinematic
High-Throughput LDPC decoders
- IEEE Trans. on Very Large Scale Integration Systems
, 2003
"... Abstract—A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design—namely LDPC code design, de ..."
Abstract
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Cited by 107 (1 self)
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, decoding algorithm, and decoder architecture. First, the interconnect complexity problem of current decoder implementations is mitigated by designing architecture-aware LDPC codes having embedded structural regularity features that result in a regular and scalable message-transport network with reduced
The USC Multiprocessor Testbed Project: Project Overview
, 1994
"... In multiprocessor systems, processing nodes contain a processor, some cache and a share of the system memory, and are connected through a scalable interconnect. The system memory partitions may be shared (shared-memory systems) or disjoint (messagepassing systems). Within each class of systems many ..."
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Cited by 4 (0 self)
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architectural variations are possible. Comparisons among systems are difficult because of the lack of a common hardware platform to implement the different architectures. The U.S.C. Multiprocessor Testbed is a hardware emulator for the rapid prototyping of vastly different multiprocessor systems. In the testbed
Interconnection of geographically distributed wireless mesh testbeds: Resource sharing on a large scale
"... a b s t r a c t Creating large scale testbeds for evaluating wireless mesh technologies and protocols, and for testing their ability to support real world applications in realistic environments, is a crucial step towards the ultimate success of the WMN paradigm. In this paper we suggest the hierarc ..."
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the hierarchical federation of a planetary scale infrastructure, such as PlanetLab, with a number of local OMF-based wireless testbeds as a viable approach towards this goal. Along such direction, we present an architectural model for integrating at the technical level these two kinds of infrastructures and our
Interconnecting Ad Hoc Networks to Fixed Internet: Test-bed Implementation and Experimental Evaluation
"... It is widely recognized that a prerequisite for the commercial penetration of the ad hoc networking technologies is the integration with existing wired/wireless infrastructure-based networks to provide an easy and transparent access to the Internet and its services. However, most of the existing sol ..."
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solutions for enabling the interconnection between IPv4-based mobile ad hoc networks and the Internet are based on complex and inefficient mechanisms, as Mobile-IP and IP tunnelling. In this paper, we describe an alternative approach to build multi-hop and heterogeneous proactive ad hoc networks, which can
A Gigabit Local ATM Testbed for Multimedia Applications
, 1996
"... This document details the design specifications for a high speed multicast virtual circuit switch being developed at Washington University. A prototype implementation of this switching fabric forms an important component of a bigger project, whose goal is the investigation and development of two key ..."
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Cited by 12 (4 self)
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(ARL) and the Advanced Networks Group (ANG), both of which are groups in the Department of Computer Science at Washington University. The innovative aspects of the switch architecture described in this document include: a novel cell recycling architecture, a nonblocking design that is asymptotically
Results 1 - 10
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170
