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78
Mapping Neural Networks onto MessagePassing Multicomputers
, 1989
"... This paper investigates the architectural requirements for simulating neural networks using massively parallel multiprocessors. First, we model the connectivity patterns in large neural networks. A distributed processor/memory organization is developed for efficiently simulating asynchronous, value ..."
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Cited by 23 (13 self)
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, and the optimal number and granularity of processors needed to meet a particular cost/performance goal. The suitability of existing computers is assessed in the light of estimated architectural demands. The structural model offers an efficient methodology for mapping virtual neural networks onto a real parallel
Spinnaker: mapping neural networks onto a massivelyparallel chip multiprocessor
 In Neural networks, 2008. ijcnn 2008.(ieee world congress on computational intelligence). IEEE international joint conference on
, 2008
"... Abstract—SpiNNaker is a novel chip – based on the ARM processor – which is designed to support large scale spiking neural networks simulations. In this paper we describe some of the features that permit SpiNNaker chips to be connected together to form scalable massivelyparallel systems. Our eventu ..."
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Cited by 35 (9 self)
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tual goal is to be able to simulate neural networks consisting of 109 neurons running in ‘real time’, by which we mean that a similarly sized collection of biological neurons would run at the same speed. In this paper we describe the methods by which neural networks are mapped onto the system, and how
Execution Of Neural Network Algorithms On An Array Of BitSerial Processors
 Pattern Recognition, Comp. Arch. for Vision and Pattern Recognition
, 1990
"... Large processor arrays are candidates for performing computations of neural network models at speeds required for real time applications, e.g. in pattern recognition. The paper gives a general model of an array of bitserial processors and demonstrates the mapping of neural net models on such an arr ..."
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Cited by 6 (1 self)
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Large processor arrays are candidates for performing computations of neural network models at speeds required for real time applications, e.g. in pattern recognition. The paper gives a general model of an array of bitserial processors and demonstrates the mapping of neural net models
Mapping Parallel Distributed Knowledge Models onto Asynchronous Recurrent Logic Arrays
"... An approach was developed to create asynchronous recurrent logic arrays for the binary neural networks used as parallel distributed knowledge models. This approach converts the neurons in a neural network model into recurrent switching functions. These recurrent switching functions are then mapped o ..."
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An approach was developed to create asynchronous recurrent logic arrays for the binary neural networks used as parallel distributed knowledge models. This approach converts the neurons in a neural network model into recurrent switching functions. These recurrent switching functions are then mapped
CoarseGrained Processor Array Implementing the Multilayer Neural Networks Model
, 1990
"... Fast digital simulators are essential tools for research and development of neural networks (NN). Among the available NN models, the Multi Layer Perceptton (MLP) is one of the most widely used. Thus an important research goal is to find a digital architecture to efficiently implement MLP neural netw ..."
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Cited by 1 (1 self)
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networks. In this paper a coarse grained processor array is proposed, which tries to overcome the previous limitations when a network composed by many neurons has to be mapped into a limited number of processors (PE). Given the total number of PEs, the proposed architecture can be configured to inplement
A 0.8 m CMOS TwoDimensional Programmable MixedSignal FocalPlane Array Processor with OnChip Binary Imaging and Instructions Storage
"... Abstract—This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of twodimensional (2D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7b accuracy. The internal programming si ..."
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Cited by 2 (0 self)
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/nonlinear network universal machine (CNNUM). It has been fabricated in a 0.8 m singlepoly doublemetal technology and features 2 s operation speed (time required to process an image) and around 7b accuracy in the analog processing operations. Index Terms — Analog array processors, cellular neural networks
Heuristic and neural algorithms for mapping tasks to a reconfigurable array
"... We consider the problem of mapping tasks onto processors in a reconfigurable array architecture. We assume a directed acyclic task graph as input. The node weights in the task graph represent their computational requirement; the weight on an edge (i, j> is an estimate of the communication require ..."
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Cited by 1 (0 self)
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We consider the problem of mapping tasks onto processors in a reconfigurable array architecture. We assume a directed acyclic task graph as input. The node weights in the task graph represent their computational requirement; the weight on an edge (i, j> is an estimate of the communication
Cellular Neural Networks for Segmentation of Image Sequence
"... The Cellular Neural Networks (CNN) model is now a paradigm of cellular analog programmable multidimensional processor array with distributed local logic and memory. CNNs consist of many parallel analogue processors computing in real time. One desirable feature is that these processors arranged in a ..."
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Cited by 3 (0 self)
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The Cellular Neural Networks (CNN) model is now a paradigm of cellular analog programmable multidimensional processor array with distributed local logic and memory. CNNs consist of many parallel analogue processors computing in real time. One desirable feature is that these processors arranged in a
Neural Network Modeling of DiscreteTime Chaotic Maps
"... Although chaotic systems have received increasing attention over the past two decades, traditional modeling tools have always encountered considerable analytical and numerical difficulties in modeling and predicting the behavior of chaotic systems. Neural networks, on the other hand, seem to be able ..."
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to be able to introduce a powerful modeling tool relying on their nonlinear nature. This paper contains a brief discussion on the properties of one and twodimensional discrete maps, an introduction to the operation of perceptron neural networks, neural network modeling and prediction of consecutive samples
The Ring Array Processor (RAP): Algorithms and Architecture
, 1990
"... In our speech recognition research, we have been experimenting with layered "neural" algorithms as probabilistic estimators for a Hidden Markov Model (HMM) procedure [1][3]. Features representing the spectral content of the speech are estimated 100 times per second. A layered netw ..."
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Cited by 1 (0 self)
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layers are used. For others, the speech features are vectorquantized to map the frame into one of a set of prototype vectors, and the network input consists of a binary input neuron for each possible feature value, only one of which can be active at atime. In either case, the neural network is trained
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