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42
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors
- In Proc. Design, Automation and Test Europe
, 2003
"... Software implementations of channel decoding algo-rithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibility and extensibility. For high throughput, however, a single processor can not provide the necessary compute power. Usin ..."
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Cited by 12 (1 self)
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Software implementations of channel decoding algo-rithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibility and extensibility. For high throughput, however, a single processor can not provide the necessary compute power
Parallel Interleaver Design and VLSI Architecture for Low Latency Map Turbo Decoders
- IEEE Transactions on VLSI Systems
, 2005
"... Abstract—Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly ..."
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Cited by 14 (0 self)
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Abstract—Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating
R.Ginosar,“Parallel VLSI architectures and parallel interleaving design for low-latency MAP turbo decoders”,Tech.Rep.CCITTR436
"... Abstract- Standard VLSI implementation of turbo decoding requires substantial memory and incurs a long latency, which cannot be tolerated in some applications. A novel parallel VLSI architecture for low-latency turbo decoding is described, comprising multiple SISO elements, operating jointly on one ..."
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Cited by 3 (1 self)
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Abstract- Standard VLSI implementation of turbo decoding requires substantial memory and incurs a long latency, which cannot be tolerated in some applications. A novel parallel VLSI architecture for low-latency turbo decoding is described, comprising multiple SISO elements, operating jointly on one
Advance Turbo Encoder and Turbo Decoder
"... Abstract- This paper presents the design and development of an efficient VLSI architecture for 3GPP advanced Turbo decoder by utilizing the convolutional interleaver. The high-throughput 3GPP Advance Turbo code requires turbo decoder architecture. Interleaver is known to be the main obstacle to the ..."
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Abstract- This paper presents the design and development of an efficient VLSI architecture for 3GPP advanced Turbo decoder by utilizing the convolutional interleaver. The high-throughput 3GPP Advance Turbo code requires turbo decoder architecture. Interleaver is known to be the main obstacle
Sora: High Performance Software Radio Using General Purpose Multi-core Processors
"... This paper presents Sora, a fully programmable software radio platform on commodity PC architectures. Sora combines the performance and fidelity of hardware SDR platforms with the programmability and flexibility of general-purpose processor (GPP) SDR platforms. Sora uses both hardware and software t ..."
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Cited by 49 (5 self)
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techniques to address the challenges of using PC architectures for highspeed SDR. The Sora hardware components consist of a radio front-end for reception and transmission, and a radio control board for high-throughput, low-latency data transfer between radio and host memories. Sora makes extensive use
High Throughput Low Latency LDPC Decoding on GPU for... SDR Systems
"... Abstract—In this paper, we present a high throughput and low latency LDPC (low-density parity-check) decoder implementation on GPUs (graphics processing units). The existing GPU-based LDPC decoder implementations suffer from low throughput and long latency, which prevent them from being used in prac ..."
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Cited by 4 (1 self)
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Abstract—In this paper, we present a high throughput and low latency LDPC (low-density parity-check) decoder implementation on GPUs (graphics processing units). The existing GPU-based LDPC decoder implementations suffer from low throughput and long latency, which prevent them from being used
A Low Latency SISO with Application to Broadband Turbo Decoding
- IEEE J. SELECT. AREAS COMMUN
, 2001
"... The standard algorithm for computing the soft-inverse of a finite-state machine [i.e., the soft-in/soft-out (SISO) module] is the forward--backward algorithm. These forward and backward recursions can be computed in parallel, yielding an architecture with latency ( ), where is the block size. We dem ..."
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Cited by 5 (2 self)
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latency (log 2 ). The decrease in latency comes primarily at a cost of area with, in some cases, only a marginal increase in computation. We discuss how this structure could be used to design a very high throughput turbo decoder or, more generally, an iterative detector. Various subwindowing and tiling
Area-Efficient High Speed Decoding Schemes For Turbo/map Decoders
- Proc. IEEE ICASSP
, 2001
"... Turbo decoders inherently have a large latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, two types of area-efficient ..."
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Turbo decoders inherently have a large latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, two types of area
Design of a High-Speed Asynchronous Turbo Decoder, ASYNC
, 2007
"... This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-performance error correction codes used in applications where maximal information transfer is needed over a limitedbandwidth ..."
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Cited by 1 (0 self)
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This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-performance error correction codes used in applications where maximal information transfer is needed over a limitedbandwidth
New Algorithms for High-Throughput Decoding with Low-Density Parity-Check Codes using Fixed-Point SIMD Processors
, 2012
"... Most digital signal processors contain one or more functional units with a single-instruction, multiple-data architecture that supports saturating fixed-point arith-metic with two or more options for the arithmetic precision. The processors designed for the highest performance contain many such func ..."
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introduces a latency that can also limit the algorithm’s throughput. In this dissertation, we consider the turbo-decoding message-passing algorithm for iterative decoding of low-density parity-check codes and investigate its perfor-mance in parallel execution on a processor of interconnected functional units
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