### TABLE II 100NM SIMULATION RESULTS FOR LOW-POWER DESIGN

### Table 2.1 Table include names of different low-power microprocessors and whether the micro- processors are support by GNU.

2004

### Table 2.1 Table include names of different low-power microprocessors and whether the micro- processors are support by GNU.

2004

### Table 1. Low Power Techniques at Different Levels in the Design Cycle

### Table 1: Comparison of hardware cost for the DCT and IDCT architectures with their low-power designs in terms of 2-input multipliers and 2-input adders.

1995

"... In PAGE 15: ... Also, we will compare the proposed multirate SIPO architectures with the existing SIPO and PIPO architectures [3][14]. Table1 summarizes the hardware cost for all the proposed architectures under normal operation and under multirate operation (M = 2; 4). As we can see, the hardware overhead of the low-power design is linear complexity increase for the speed compensation.... ..."

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### Table 2: Comparison of hardware cost for the MLT and ELT with their low-power designs in terms of 2-input multipliers and 2-input adders.

1995

"... In PAGE 8: ... Hence, the MLT module can operate at the half of the original frequency by doubling the hardware complexity. The comparison of hardware cost is shown in Table2 . Suppose that P0 denotes the power consumption of the MLT module in Fig.... In PAGE 9: ... Hence, we can compute the 0th and (N ? 1)th ELT coe cients from XELT;0 (t) = ?XS;1(t) + p2XC;0(t) ? XS;?1(t); XELT;N?1 (t) = ?XS;N?1(t) + p2XC;N?1(t) + XS;N?2(t); (24) instead of implementing two extra ELT modules for XS;?1(t) and XS;N(t). The hardware cost for the ELT can be found in Table2 . Since the number of multipliers of the ELT is about the same as that of the MLT, the power savings for both transforms are similar.... ..."

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### Table 3. TE energy consumption for tests of Figure 6. The energy numbers given are in fJ per clock cycle. For the low-power TE designs, the minimum energy for each test is shown in bold.

2001

Cited by 12

### Table 4: Optimal wordlength assignment under the constraint SNR = 40dB, where BA is the average wordlength. (a) Normal IIR DCT. (b) Low-power DCT with M = 2.

1995

"... In PAGE 15: ...14 where the fact that [13] Ef(XDCT;k(t))2g = Efx2(t)g = 1=3; k = 1; 2; : : : ; N ? 1; (48) is used. If we want to achieve a performance of 40 dB in SNR for the kth DCT component, the optimal wordlength Bk for that channel can be computed from (47) as Bk = 2 6 6 6 4 ? log10[sin2(2!k) 8 N(Ns(k)+1)] 2 log10 2 + K 3 7 7 7 : (49) As an example, the Bk apos;s for the case N = 8 and 16 under the constraint SNR = 40 dB are listed in Table4 (a), where BA denotes the average system wordlength. As we can see, BA = 12 bit is su cient to meet the accuracy criteria.... In PAGE 15: ... Suppose that the silicon area of the multiplier is dominant in the chip and the size of the multipliers is proportional to (BA)2. Using the optimal wordlengths in Table4 , we can reduce the total chip area to 56% of the original design without degrading the SNR performance. This shows that our analysis approach provides more insights to determine the architectural speci cations than the experimental approach.... In PAGE 17: ... The overall D can be found from the summation of the two dynamic ranges, which is given by (see Appendix) D1 = 2C(k) (j cos !kj + j cos 3!kj) ; D2 = C(k) N=2?1 X n=0 (jcos[(4n + 1)!k]j + jcos[(4n + 3)!k]j) ; D = maxfD1; D2g: (56) Using the analytical results in (55) and (56), we can also nd the optimal wordlengths for N = 8 and 16 under the 40dB SNR constraint. The results are listed in Table4 (b). It is interesting to note that the average wordlengths of the multirate DCT architectures are even less than those of the normal DCT architectures.... ..."

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### Table 1. Bluetooth low-power mode measurements

2003

"... In PAGE 5: ... They can be activated once a connection exists between Bluetooth devices. Transition times and average power dissipation for switching between the modes are shown in Table1 . The CSR Bluetooth chips also supports deep sleep state with only 270uW power consumption [15].... ..."

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