Results 1 - 10
of
101
Fault tolerance overhead in network-on-chip flow control schemes
- In Proceedings of the SBCCI Conference 2005
, 2005
"... Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer management and allocation are fundamental tasks of each flow control scheme. Buffered flow control is the focus of this work. We ..."
Abstract
-
Cited by 25 (7 self)
- Add to MetaCart
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer management and allocation are fundamental tasks of each flow control scheme. Buffered flow control is the focus of this work. We
Supporting task migration in multi-processor systems-on-chip: a feasibility study
- Proc
, 2006
"... With the advent of multi-processor systems-on-chip, the interest in process migration is again on the rise both in research and in product development. New challenges associated with the new scenario include increased sensitivity to implementation complexity, tight power budgets, requirements on exe ..."
Abstract
-
Cited by 29 (1 self)
- Add to MetaCart
for the constraints of single chip multiprocessors with distributed operating systems. Load balancing in the system is maintained by means of intelligent initial placement and task migration. We propose a user-managed migration scheme based on code checkpointing and user-level middleware support as an effective
Stack Frames Placement in Scratch-Pad Memory for Energy Reduction of Multi-task Applications∗
"... Scratch-pad memories (SPM) are small on-chip mem-ory devices whose access is much faster and consumes much less energy than off-chip memories. While SPM are usually too small for containing all the code or data of an application, significant energy consumption re-ductions can be achieved by assignin ..."
Abstract
- Add to MetaCart
Scratch-pad memories (SPM) are small on-chip mem-ory devices whose access is much faster and consumes much less energy than off-chip memories. While SPM are usually too small for containing all the code or data of an application, significant energy consumption re-ductions can be achieved
Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support
"... Abstract—In today’s multiprocessor SoCs (MPSoCs), parallel programming models are needed to fully exploit hardware capabilities programming models onto tightly power-constrained hardware architectures imposes overheads which might seriously compromise performance and energy efficiency. The objective ..."
Abstract
-
Cited by 1 (0 self)
- Add to MetaCart
support. Index Terms—MPSoCs, embedded multimedia, programming models, task-level parallelism, energy efficiency, low power. 1
Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms
"... Abstract — Dynamic variations in application functionality and performance requirements can lead to the imposition of widely disparate requirements on System-on-Chip (SoC) platform hardware over time. This has led to interest in the design and use of adaptive SoC platforms that are capable of provid ..."
Abstract
-
Cited by 1 (0 self)
- Add to MetaCart
task. In this work, we focus on two configurable subsystems of SoC platforms that play a crucial role in determining overall system performance, namely, the on-chip communication architecture, and the on-chip memory architecture. Using detailed case studies, we demonstrate the limitations of designs
An Efficient Programmable 10 Gigabit Ethernet Network Interface Card
- In Proc. of HPCA
, 2005
"... This paper explores the hardware and software mechanisms necessary for an efficient programmable 10 Gigabit Ethernet network interface card. Network interface processing requires support for the following characteristics: a large volume of frame data, frequently accessed frame metadata, and high fra ..."
Abstract
-
Cited by 31 (5 self)
- Add to MetaCart
frame rate processing. This paper proposes three mechanisms to improve programmable network interface efficiency. First, a partitioned memory organization enables low-latency access to control data and highbandwidth access to frame contents from a high-capacity memory. Second, a novel distributed task
Congestion-aware task mapping in NoCbased MPSoCs with dynamic workload
- in Proc. ISVLSI, 2007
"... Applications running in heterogeneous MPSoCs, as mul-timedia and networking, normally contain a dynamic work-load of tasks. This implies a varying number of tasks simul-taneously running, with their number possibly exceeding the available resources. This may require the execution of task mapping at ..."
Abstract
-
Cited by 2 (0 self)
- Add to MetaCart
to minimize NoC congestion. Without loss of generality, heterogeneous MPSoC archi-tectures may be represented, as a set of processing nodes that interact via a communication network. Processing nodes may support either hardware or software task execution. Hardware tasks execute in reconfigurable logic
A tuneable software cache coherence protocol for heterogeneous MPSoCs
- in Proceedings of CODES+ISSS ’09. ACM
"... ABSTRACT In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing hardware cache coherence protocols are less suitable for MPSoCs because many off-the-shelf processors used in MPSo ..."
Abstract
-
Cited by 2 (1 self)
- Add to MetaCart
ABSTRACT In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing hardware cache coherence protocols are less suitable for MPSoCs because many off-the-shelf processors used
Software reverse engineering as a sensemaking task (in press).
- Journal of Information Assurance and Security.
, 2012
"... Abstract: Software reverse engineering involves analyzing computer program executables to understand their structure, functionality, and behavior. In this paper, common reverse engineering functions are decomposed to isolate the information-processing and sensemaking subtasks involved. This paper r ..."
Abstract
-
Cited by 2 (2 self)
- Add to MetaCart
include naming concepts, assigning concepts to locations in the code, and recognizing assigned concept locations VII. Knowledge Modeling for Reverse Engineering In order to understand the automation needs that would support reverse engineering tasks, it is important to develop knowledge requirements
Guaranteeing Communication Quality in Real World WSN Deployments
"... April 29, 2011Für UnsShe had never before seen a rabbit with either a waistcoat-pocket, or a watch to take out of it, and burning with curiosity, she ran across the field after it Lewis CarrollThe following document, written under the supervision of Dr. reviewed by: ..."
Abstract
- Add to MetaCart
April 29, 2011Für UnsShe had never before seen a rabbit with either a waistcoat-pocket, or a watch to take out of it, and burning with curiosity, she ran across the field after it Lewis CarrollThe following document, written under the supervision of Dr. reviewed by:
Results 1 - 10
of
101