Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer management and allocation are fundamental tasks of each flow control scheme. Buffered flow control is the focus of this work. We

for the constraints of single chip multiprocessors with distributed operating systems. Load balancing in the system is maintained by means of intelligent initial placement and task migration. We propose a user-managed migration scheme based on code checkpointing and user-level middleware support as an effective

Scratch-pad memories (SPM) are small on-chip mem-ory devices whose access is much faster and consumes much less energy than off-chip memories. While SPM are usually too small for containing all the code or data of an application, significant energy consumption re-ductions can be achieved

support. Index Terms—MPSoCs, embedded multimedia, programming models, task-level parallelism, energy efficiency, low power. 1

task. In this work, we focus on two configurable subsystems of SoC platforms that play a crucial role in determining overall system performance, namely, the on-chip communication architecture, and the on-chip memory architecture. Using detailed case studies, we demonstrate the limitations of designs

frame rate processing. This paper proposes three mechanisms to improve programmable network interface efficiency. First, a partitioned memory organization enables low-latency access to control data and highbandwidth access to frame contents from a high-capacity memory. Second, a novel distributed task

to minimize NoC congestion. Without loss of generality, heterogeneous MPSoC archi-tectures may be represented, as a set of processing nodes that interact via a communication network. Processing nodes may support either hardware or software task execution. Hardware tasks execute in reconfigurable logic

ABSTRACT In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing hardware cache coherence protocols are less suitable for MPSoCs because many off-the-shelf processors used

include naming concepts, assigning concepts to locations in the code, and recognizing assigned concept locations VII. Knowledge Modeling for Reverse Engineering In order to understand the automation needs that would support reverse engineering tasks, it is important to develop knowledge requirements

April 29, 2011Für UnsShe had never before seen a rabbit with either a waistcoat-pocket, or a watch to take out of it, and burning with curiosity, she ran across the field after it Lewis CarrollThe following document, written under the supervision of Dr. reviewed by: