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Logics of communication and change
 Information and Computation
, 2005
"... Current dynamic epistemic logics often become cumbersome and opaque when common knowledge is added for groups of agents. Still, postconditions regarding common knowledge express the essence of what communication achieves. We propose new systems that extend the underlying static epistemic languages i ..."
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Cited by 123 (54 self)
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Current dynamic epistemic logics often become cumbersome and opaque when common knowledge is added for groups of agents. Still, postconditions regarding common knowledge express the essence of what communication achieves. We propose new systems that extend the underlying static epistemic languages
The polyadic πcalculus: a tutorial
 LOGIC AND ALGEBRA OF SPECIFICATION
, 1991
"... The πcalculus is a model of concurrent computation based upon the notion of naming. It is first presented in its simplest and original form, with the help of several illustrative applications. Then it is generalized from monadic to polyadic form. Semantics is done in terms of both a reduction syste ..."
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Cited by 187 (1 self)
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The πcalculus is a model of concurrent computation based upon the notion of naming. It is first presented in its simplest and original form, with the help of several illustrative applications. Then it is generalized from monadic to polyadic form. Semantics is done in terms of both a reduction
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
, 2004
"... This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make `new' compound standard cells, ..."
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Cited by 129 (16 self)
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, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.
A transformation based algorithm for reversible logic synthesis
 in Design Automation Conf
"... A digital combinational logic circuit is reversible if it maps each input pattern to a unique output pattern. Such circuits are of interest in quantum computing, optical computing, nanotechnology and lowpower CMOS design. Synthesis approaches are not well developed for reversible circuits even for ..."
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Cited by 107 (23 self)
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A digital combinational logic circuit is reversible if it maps each input pattern to a unique output pattern. Such circuits are of interest in quantum computing, optical computing, nanotechnology and lowpower CMOS design. Synthesis approaches are not well developed for reversible circuits even
Light Affine Logic
 ACM TRANSACTIONS ON COMPUTATIONAL LOGIC
, 1998
"... Much effort has been recently devoted to the study of polytime formal (and especially logical) systems [GSS92, LM93, Le94, Gi96]. The purpose of such systems is manyfold. On the theoretical side, they provide a better understanding of what is the logical essence of polytime reduction (and other comp ..."
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Cited by 88 (6 self)
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Much effort has been recently devoted to the study of polytime formal (and especially logical) systems [GSS92, LM93, Le94, Gi96]. The purpose of such systems is manyfold. On the theoretical side, they provide a better understanding of what is the logical essence of polytime reduction (and other
LowLatency VirtualChannel Routers for OnChip Networks
 In International Symposium on Computer Architecture
, 2004
"... The onchip communication requirements of many systems are best served through the deployment of a regular chipwide network. This paper presents the design of a lowlatency onchip network router for such applications. We remove control overheads (routing and arbitration logic) from the critical pa ..."
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Cited by 148 (1 self)
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The onchip communication requirements of many systems are best served through the deployment of a regular chipwide network. This paper presents the design of a lowlatency onchip network router for such applications. We remove control overheads (routing and arbitration logic) from the critical
It Usually Works: The Temporal Logic of Stochastic Systems
, 1995
"... . In this paper the branching time logic pCTL is defined. pCTL expresses quantitative bounds on the probabilities of correct behavior; it can be interpreted over discrete Markov processes. A bisimulation relation is defined on finite Markov processes, and shown to be sound and complete with re ..."
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Cited by 103 (0 self)
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. In this paper the branching time logic pCTL is defined. pCTL expresses quantitative bounds on the probabilities of correct behavior; it can be interpreted over discrete Markov processes. A bisimulation relation is defined on finite Markov processes, and shown to be sound and complete
The πcalculus as a theory in linear logic: Preliminary results
 3rd Workshop on Extensions to Logic Programming, LNCS 660
, 1993
"... The agent expressions of the πcalculus can be translated into a theory of linear logic in such a way that the reflective and transitive closure of πcalculus (unlabeled) reduction is identified with “entailedby”. Under this translation, parallel composition is mapped to the multiplicative disjunct ..."
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Cited by 113 (18 self)
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The agent expressions of the πcalculus can be translated into a theory of linear logic in such a way that the reflective and transitive closure of πcalculus (unlabeled) reduction is identified with “entailedby”. Under this translation, parallel composition is mapped to the multiplicative
On Uniformity Within NC 1
 Journal of Computer and System Sciences
, 1990
"... In order to study circuit complexity classes within NC 1 in a uniform setting, we need a uniformity condition which is more restrictive than those in common use. Two such conditions, stricter than NC 1 uniformity [Ru81,Co85], have appeared in recent research: Immerman's families of circuits ..."
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Cited by 150 (11 self)
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of circuits defined by firstorder formulas [Im87a,Im87b] and a uniformity corresponding to Buss' deterministic logtime reductions [Bu87]. We show that these two notions are equivalent, leading to a natural notion of uniformity for lowlevel circuit complexity classes. We show that recent results
Costeffective approach for reducing soft error failure rate in logic circuits
, 2003
"... In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic circuit. Rather than target all modeled faults, CED is targeted towards the nodes that have the highe ..."
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Cited by 108 (8 self)
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In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic circuit. Rather than target all modeled faults, CED is targeted towards the nodes that have
Results 11  20
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3,900