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110
Parallel sparse matrixvector and matrixtransposevector multiplication using compressed sparse blocks
 IN SPAA
, 2009
"... This paper introduces a storage format for sparse matrices, called compressed sparse blocks (CSB), which allows both Ax and A T x to be computed efficiently in parallel, where A is an n × n sparse matrix with nnz ≥ n nonzeros and x is a dense nvector. Our algorithms use Θ(nnz) work (serial running ..."
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Cited by 26 (1 self)
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This paper introduces a storage format for sparse matrices, called compressed sparse blocks (CSB), which allows both Ax and A T x to be computed efficiently in parallel, where A is an n × n sparse matrix with nnz ≥ n nonzeros and x is a dense nvector. Our algorithms use Θ(nnz) work (serial running
Experiences with the Sparse MatrixVector Multiplication on a Manycore Processor
"... Abstract—Industry is moving towards manycore processors, which are expected to consist of tens or even hundreds of cores. One of these future processors is the 48core experimental processor SingleChip Cloud Computer (SCC). The SCC was created by Intel Labs as a platform for manycore research. Th ..."
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. The characteristics of this system turns it into a big challenge for researchers in order to extract performance from such complex architecture. In this work we study and explore the behavior of an irregular application such as the Sparse MatrixVector multiplication (SpMV) on the SCC processor. An evaluation
Efficient sparse matrixvector multiplication on CUDA
, 2008
"... The massive parallelism of graphics processing units (GPUs) offers tremendous performance in many highperformance computing applications. While dense linear algebra readily maps to such platforms, harnessing this potential for sparse matrix computations presents additional challenges. Given its rol ..."
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Cited by 113 (2 self)
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role in iterative methods for solving sparse linear systems and eigenvalue problems, sparse matrixvector multiplication (SpMV) is of singular importance in sparse linear algebra. In this paper we discuss data structures and algorithms for SpMV that are efficiently implemented on the CUDA platform
Parallel Sparse MatrixVector Multiplication
, 1997
"... In this paper we describe an algorithm for unstructured sparse matrixvector multiplication on distributed memory parallel computers. We focus on both local and global computational efficiency, i.e. single processor computational performance and interprocessor communication efficiency. Numerical ex ..."
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Cited by 2 (0 self)
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In this paper we describe an algorithm for unstructured sparse matrixvector multiplication on distributed memory parallel computers. We focus on both local and global computational efficiency, i.e. single processor computational performance and interprocessor communication efficiency. Numerical
Sparse matrixvector multiplication on FPGAs
 In Proceedings of the ACM International Symposium on Field Programmable Gate Arrays
, 2005
"... Sparse matrixvector multiplication (SpMXV) is a key computational kernel widely used in scientific applications and signal processing applications. However, the performance of SpMXV on most modern processors is poor due to the irregular sparsity structure in the matrices. Applicationspecific proce ..."
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Cited by 60 (7 self)
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Sparse matrixvector multiplication (SpMXV) is a key computational kernel widely used in scientific applications and signal processing applications. However, the performance of SpMXV on most modern processors is poor due to the irregular sparsity structure in the matrices. Application
Implementing sparse matrixvector multiplication on throughputoriented processors
 In SC ’09: Proceedings of the 2009 ACM/IEEE conference on Supercomputing
, 2009
"... Sparse matrixvector multiplication (SpMV) is of singular importance in sparse linear algebra. In contrast to the uniform regularity of dense linear algebra, sparse operations encounter a broad spectrum of matrices ranging from the regular to the highly irregular. Harnessing the tremendous potential ..."
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Cited by 142 (7 self)
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Sparse matrixvector multiplication (SpMV) is of singular importance in sparse linear algebra. In contrast to the uniform regularity of dense linear algebra, sparse operations encounter a broad spectrum of matrices ranging from the regular to the highly irregular. Harnessing the tremendous
Sparse MatrixVector Multiplication on FPGAs
, 2007
"... Floatingpoint Sparse MatrixVector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices significantly reduces the performance of SpMXV on generalpurpose processors, which rely heavily on the cache hierarchy to ac ..."
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Floatingpoint Sparse MatrixVector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices significantly reduces the performance of SpMXV on generalpurpose processors, which rely heavily on the cache hierarchy
Efficient Sparse MatrixVector Multiplication on x86based Manycore Processors
 In 27th International Conference on Supercomputing (ICS
"... Sparse matrixvector multiplication (SpMV) is an important kernel in many scientific applications and is known to be memory bandwidth limited. On modern processors with wide SIMD and large numbers of cores, we identify and address several bottlenecks which may limit performance even before memory b ..."
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Cited by 14 (0 self)
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Sparse matrixvector multiplication (SpMV) is an important kernel in many scientific applications and is known to be memory bandwidth limited. On modern processors with wide SIMD and large numbers of cores, we identify and address several bottlenecks which may limit performance even before memory
Vector ISA Extension for Sparse MatrixVector Multiplication
"... . In this paper we introduce a vector ISA extension to facilitate sparse matrix manipulation on vector processors (VPs). First we introduce a new Block Based Compressed Storage (BBCS) format for sparse matrix representation and a Blockwise Sparse MatrixVector Multiplication approach. Additionally, ..."
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. In this paper we introduce a vector ISA extension to facilitate sparse matrix manipulation on vector processors (VPs). First we introduce a new Block Based Compressed Storage (BBCS) format for sparse matrix representation and a Blockwise Sparse MatrixVector Multiplication approach. Additionally
Vector ISA Extension for Sparse MatrixVector Multiplication
"... . In this paper we introduce a vector ISA extension to facilitate sparse matrix manipulation on vector processors (VPs). First we introduce a new Block Based Compressed Storage (BBCS) format for sparse matrix representation and a Blockwise Sparse MatrixVector Multiplication approach. Additionally, ..."
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. In this paper we introduce a vector ISA extension to facilitate sparse matrix manipulation on vector processors (VPs). First we introduce a new Block Based Compressed Storage (BBCS) format for sparse matrix representation and a Blockwise Sparse MatrixVector Multiplication approach. Additionally
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