, or JavaScript. Next, we show how the resulting transducers, post-exploration, fit into a recent advance in data-parallel compilation of finite state machines. Finally, we describe a concrete implementation built on the Windows High Perfor-mance Computing framework in a cluster. We have implemented our

to generate high per-formance inference code. In turn, on modern architectures, high performance re-quires parallel execution. In this paper we present Augur, a probabilistic modeling language and compiler for Bayesian networks designed to make effective use of data-parallel architectures such as GPUs. We

Abstract – The Cell BE processor is capable of achieving very high levels of performance via parallel computation. The processors in video accelerators, known as GPUs, are also high performance parallel processors. The RapidMind Development Platform provides a simple data-parallel model

Abstract – The Cell BE processor is capable of achieving very high levels of performance via parallel computation. The processors in video accelerators, known as GPUs, are also high performance parallel processors. The RapidMind Development Platform provides a simple data-parallel model

In data-parallel languages such as High Performance Fortran and Fortran D, arrays are mapped to processors through a two step process involving alignment followed by distribution. A compiler that generates code for each processor has to compute the sequence of local memory addresses accessed

at stateof-the-art beamlines. New high-performance computing algorithms, codes, and software tools have been developed to analyze GISAXS images generated at synchrotron light sources. We have implemented a flexible GISAXS simulation code based on the Distorted Wave Born Approximation (DWBA) written in C

-automated approaches have been proposed to automatically generate hardware-level codes from high-level sequential sources. Polyhedral models are becoming more popular because of their combination of expressiveness, compactness, and accurate abstraction of the data-parallel behaviour of programs. These models provide

Purely functional, embedded array programs are a good match for SIMD hardware, such as GPUs. However, the naive compilation of such programs quickly leads to both code explosion and an excessive use of intermediate data structures. The resulting slowdown is not acceptable on target hardware

Writing high performance GPGPU code is often difficult and time-consuming, potentially requiring laborious manual tuning of low-level details. Despite these challenges, the cost in ignoring GPUs in high performance computing is increasingly large. Auto-tuning is a potential solution to the problem

Abstract The key principles of the Application-Specific Processor Design (ASPD) methodology include: a semi-custom compilation-driven design/implementation approach, the exploitation of fine-grained parallelism for high performance. and the adaptation of datapath topology to the data transfers