and efficiently communicate data between accelerator memories. In this paper, we extend this work with techniques to perform efficient data movement between accelerators within the same node using a DMA-assisted, peer-to-peer intranode communication technique that was recently introduced for NVIDIA GPUs. We

-chip mem-ory bank conflicts on system throughput, by decoupling bank conflicts from pipeline stalls. Simulation results show that our proposed elastic pipeline together with the co-designed bank-conflict aware warp scheduling reduces the pipeline stalls by up to 64.0 % (with 42.3 % on average) and improves

introducing extra memory divergence. We consider (1) co-issuing instructions from different divergent paths of the same warp and (2) coissuing instructions from different warps. To support (1), we introduce a novel thread reconvergence technique that ensures threads are run back in lockstep at controlflow

transparent memory management and PCI-e data transfer techniques, and dynamic slicing and scheduling techniques for kernel executions. With slicing, Kernelet divides a GPU kernel into multiple sub-kernels (namely slices). Each slice has tunable occupancy to allow co-scheduling with other slices for high GPU

Abstract—Control and memory divergence between threads within the same execution bundle, or warp, have been shown to cause significant performance bottlenecks for GPU applications. In this paper, we exploit the observation that many GPU applications exhibit error tolerance to propose branch

ultrasound scanners. This makes ultrasound the modality of choice for intraoperative use and enables image guided surgery (e.g. neuro- or laparoscopic) where surgical instruments are safely navigated inside the human body. Current CPU-based methods for 3D ultrasound reconstruction are time consuming

A GPU’s computing power lies in its abundant memory bandwidth and massive parallelism. However, its hardware thread schedulers, despite being able to quickly distribute computation to processors, often fail to capitalize on pro-gram characteristics effectively, achieving only a fraction of the GPU

© The Author(s) 2012. This article is published with open access at Springerlink.com Abstract One of the major problems with the GPU on-chip shared memory is bank conflicts. We analyze that the throughput of the GPU processor core is often con-strained neither by the shared memory bandwidth, nor

This paper aims to tackle two fundamental memory bottle-necks: limited off-chip bandwidth (bandwidth wall) and long access latency (memory wall). To achieve this goal, our ap-proach exploits the inherent error resilience of a wide range of applications. We introduce an approximation technique

are facilitated through the DS, while within an active node the framework implements the composite scheduling algorithm to schedule memory, CPU and bandwidth to solve the combined resource scheduling problems. In addition, a flexible active node Knowledge base system has been introduced in order to resolve