We address the problem of efficient schemes for mapping arbitrary parallel algorithms onto distributed memory message passing multiprocessors with mesh topologies. We analyze a particular mapping scheme, find the reasons for its low efficiency, and show that mapped algorithms tend to be both wider

This paper deals with efficient methods for mapping arbitrary parallel algorithms onto faulty general purpose VLSI/WSI data-driven array. First, a brief overview of several architectural designs of the array is given. Next, three directions for the algorithmic improvement of a certain mapping

Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network application domains. A remarkable difference with general multiprocessor task scheduling is that NPs are often programmed

. This paper presents a framework for automated mapping of parallel appli-cations with structured communication graphs to two and three dimensional mesh networks. We present several heuristic techniques for mapping 2D object graphs to 2D and 3D processor graphs and compare their performance with other

is modeled as a closed queueing network that (1) includes the effects of blocking and pipelining of messages in the network, (2) allows for arbitrary source-destination probability distributions, and (3) explicitly models the virtual channels used in the deadlock-free routing algorithm. The models are used

In this paper, we propose a new mapping of the Cyclic Elimination (CE) algorithm for the solution of block tridiagonal linear system of equations onto hypercube multiprocessors. Unlike the previous mapping schemes, in our mapping of the CE algorithm all communications are restricted to physically

Abstract. In this article we present a new class of high order accurate Arbitrary– Eulerian–Lagrangian (ALE) one–step WENO finite volume schemes for solving non-linear hyperbolic systems of conservation laws on moving two dimensional unstruc-tured triangular meshes. A WENO reconstruction algorithm

This paper describes a scheme for mapping the back propagation algorithm onto an MIMD computer with 2D-torus network. We propose a new strategy that allows arbitrary assignment of processors to the multiple degrees of back propagation parallelism (training set parallelism, pipelining and node

is modeled as a closed queueing network that (1) includes the effects of blocking and pipelining of messages in the network, (2) allows for arbitrary source-destination probability distributions, and (3) explicitly models the virtual channels used in the deadlock-free routing algorithm. The models

Software managed scratchpad memories (SPMs) provide improved performance and power in embedded processors by reducing re-quired hardware resources. Performance depends strongly on the scheme used to map code and data onto the SPM, but generating optimal mappings can be extremely difficult. Here we