### Table 2: Assembly Code Implementing the Digital Filter.

1997

"... In PAGE 15: ... This selection is driven by the INSTR/DATA signal generated by the sequencer. Based on this architecture, the 3-tap digital lter can be implemented with the 30 assembly instructions reported in Table2 . All instructions require two clock cycles to be executed, one for the fetch, decode and data address generation, and one for the data read or write.... ..."

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### Table 2. Simulation results for the 3 different adaptive filter implementation.

2003

"... In PAGE 5: ... 8, where the minimum mean square error of the DLMS filter converges to a higher value, with a longer convergence time than the LMS filter. Table2 shows the system attributes of the 3 different implementations at a same throughput of 22 kHz. Since it takes 1 clock cycle to process 1 input data, the clock frequency of the non-folded architectures is same as the throughput.... ..."

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### Table 2. Benchmarks sequential implementation

"... In PAGE 10: ...inear algebra, as described, e.g., in [17]. Table2 depicts the running times for the complete factorization of polynomials of growing degree. For each polynomial, this table also contains the time needed for the rst execution of steps 15 and 18 of the algorithm (i.... ..."

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### Table 2: Area, delay and energy per sample results for the pipelined architectures. Area Diff.(%) Delay(ns) Diff.(%)

"... In PAGE 3: ...1 Hybrid Arithmetic Operator Application The most efficient implementation for a Fully-Parallel Hybrid FIR filter is to use Binary adders and EXOR gates to make the conversion at the input/output data buses. Thus, there is no significant area difference between the architectures with Binary and Hybrid operators as shown in Table2 . In the Fully-Sequential and Semi-Parallel architectures, where array multiplier operators are used, Hybrid architectures present slightly more area.... In PAGE 3: ... This is due to the fact that the Hybrid multiplier presents a lower critical path. The direct application of Hybrid operators in the FIR architec- tures produces a reduction of energy per sample consumption as shown in Table2 . This is observed in the Fully-Sequential and Semi-Parallel architectures where array multipliers are used.... ..."

### Table 4: Comparisons between different architectures. This table compares VLSI architectures against a DSP implementation. Algorithm Architecture Transistors Clock Speed Data Rates/User

2000

"... In PAGE 16: ... Formation of bit-level matrix updates is much more effective and simpler to build in parallel with XNOR gates than as sequential multiplications on DSPs. Table4 compares the VLSI architectures with the DSP implementation of the multiuser chan- nel estimation and detection algorithms on a TI C67 floating-point DSP at 167 MHz. The channel estimation DSP implementation takes 50 ms for all 32 users or 0.... In PAGE 17: ...The DSP and the time-constrained VLSI architectures comparison in Table4 shows the ad- vantages of exploiting parallelism and designing efficient reduced complexity algorithms. Though the targeted real-time requirements are easily surpassed, the area estimates can be reduced for an area-time efficient architecture, which meets the real-time requirements within the same order of magnitude [16].... ..."

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### TABLE I AREA-THROUGHPUT TRADEOFFS FOR DIFFERENT MATCHED FILTER ARCHITECTURES WITH CONVENTIONAL AND ON-LINE ARITHMETIC. THE COMPARISONS PRESENTED ARE AGAINST A SIMPLE, CONVENTIONAL ARITHMETIC IMPLEMENTATION.

### Table 1. Architecture Implementation Results

1999

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### Table 9 Summary of the FPGA implementation for FIR filters ranging from 8 taps to 2048 taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

2005

"... In PAGE 82: ... Likewise, a 1024-tap hybrid DA architecture requires only 37% of LEs and the same memory over the hybrid DA-OBC. Other implementation results for randomly generated FIR filters whose sizes vary from 8 to 2048 taps are presented in Table9 . The word length of the LUT, Bc, is 18, and the base unit size, k, is 8.... In PAGE 82: ... The word length of the LUT, Bc, is 18, and the base unit size, k, is 8. Table9 clearly shows that LUT-based DA architecture can synthesize only up to 512-tap FIR filters, while the hybrid DA-OBC and the hybrid DA can synthesize 1024-tap FIR filters or more higher-order FIR filters, respectively, on the same FPGA chip. In particular, the hybrid DA architecture uses only 17% of LEs and less than 1% of the memory of an Altera Stratix EP1S80F1508C6 FPGA chip.... In PAGE 83: ... Two hybrid DA architectures require fewer LEs and less memory than the original LUT-based DA. Filter size (K) 4 16 64 128 256 512 1024 LUT-based DA LE 272 551 1639 3056 5890 11547 22862 (100%) Memory 344 1376 5504 11008 22016 44032 88064 (100%) LUT-less LE 300 667 2104 3984 7746 15259 30286 (132%) Hybrid DA-OBC Memory 56 224 896 1792 3584 7168 14336 (16%) LUT-less LE 210 367 887 1569 2946 5659 11086 (48%) Hybrid DA Memory 56 224 896 1792 3584 7168 14336 (16%) Table9 . Summary of the FPGA implementation results (Altera Stratix EP1S80F1508C6 FPGA chip) for randomly generated FIR filters, ranging from 8 taps to 2048 taps, when the Bc = 18 and k = 8.... ..."

### Table 2. Comparison of parallel and sequential implementations.

1996

"... In PAGE 3: ...That margins for improvements are smaller when better strategies are employed is conflrmed if we compare the efiective runtimes of the Chakrabarti{Yelick implementation on a 20 processor CM-5y, with the implementation by Sawada et al. (1994) on a PIM/m with 256 nodes, and with our own sequential implementation in C++ (Attardi and Traverso, 1995) on a single SparcStation5, as shown in Table2 (times are in seconds). Sawada et al.... ..."

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