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(Submitted to the IEEE Transactions on Computers)
, 1970
"... Two methods of describing and processing visual data by replacing the pattern with a series of functions are reviewed. One technique uses a Fourier-optics approach whereas the other uses a retinal-machine approach. Modifications are suggested for the Fourier-optics approach which greatly increases t ..."
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Two methods of describing and processing visual data by replacing the pattern with a series of functions are reviewed. One technique uses a Fourier-optics approach whereas the other uses a retinal-machine approach. Modifications are suggested for the Fourier-optics approach which greatly increases the power of the method. It is then shown that the functions produced by the Fourier-optics approach are related to the retinal machine functions by linear integral transforms. This latter result establishes a direct mathematical link between optical techniques and retinal machine (neurons, Over recent years a number of workers [1], [2] in the field of pattern recognition have taken a renewed interest in the fact that the two dimensional Fourier Transform (FT2) of a function f(x, y) can be conveniently obtained by optical means. This
Revised submission to IEEE Transaction on Computers
"... This paper presents a novel number system based on signed continuous valued digits. Arithmetic operations in this number system are performed using simple analog circuitry, in contrast to the conventional implementation of arithmetic units by Boolean or multiple-valued logic circuits. Unlike the lim ..."
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This paper presents a novel number system based on signed continuous valued digits. Arithmetic operations in this number system are performed using simple analog circuitry, in contrast to the conventional implementation of arithmetic units by Boolean or multiple-valued logic circuits. Unlike the limited precision offered by classical analog arithmetic circuits, the ensemble of continuous valued digits that comprises a number in this system, provides arbitrary implementation precision with standard analog circuitry. The number system also provides almost-carry-free arithmetic structures with digit level redundancy. In this paper we introduce the mathematical foundations for positive and negative numbers, addition, multiplication, redundancy, radix conversions, and also the digit value integrity for circuit implementations. Potential applications are in the area of low noise and low cross-talk circuitry for arithmetic circuits used in mixed-signal systems. Keywords:
IEEE TRANSACTIONS ON COMPUTERS, JANUARY 1974
"... If only the L values Ro through RL_1 are required, then it can be seen by comparing (15) and (11) that the new algorithm will require fewer multiplications than the FFT method if L < 11.2 (1 + log2 N) (16a) and will require fewer additions if L < 5.6 (1 + log2 N). (16b) Therefore, we conclude ..."
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If only the L values Ro through RL_1 are required, then it can be seen by comparing (15) and (11) that the new algorithm will require fewer multiplications than the FFT method if L < 11.2 (1 + log2 N) (16a) and will require fewer additions if L < 5.6 (1 + log2 N). (16b) Therefore, we conclude that the new algorithm will generally be more efficient than the FFT method if
IEEE TRANSACTIONS ON COMPUTERS, JULY 1970 Reviews of Papers in the Computer Field
"... In the design of synchronous sequential machines, various canonical realizations which make use of feedback shift registers have been developed [1], [2]. This paper attempts to extend some ofthese results to realize asynchronous machines in a similar manner. In an earlier paper by Brzozowski and Sin ..."
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In the design of synchronous sequential machines, various canonical realizations which make use of feedback shift registers have been developed [1], [2]. This paper attempts to extend some ofthese results to realize asynchronous machines in a similar manner. In an earlier paper by Brzozowski and Singh [3], in which canonical feedback-free realizations of definite machines ' were considered, the asynchronous unit delay (AUD) was introduced. TheAUD is an n-input n-output asynchronous sequential circuit in which the present value ofthe output n-tuple is equal to the value ofthe input n-tuple before the last input change. Extending the results of the earlier paper [3] it is shown that any fundamental mode asynchronous sequential machineM can be realized by a circuit offeedback indexm with one (n+m) x (n+m)AUD element and m inertial delays2 where n is the number of binary inputs and mn is the smallest integer not less than log2 S & where&is the maximum number of
IEEE TRANSACTIONS ON COMPUTERS 1 Optimizing Hardware Function Evaluation
"... Abstract — We present a methodology and an automated system for function evaluation unit generation. Our system selects the best function evaluation hardware for a given function, accuracy requirements, technology mapping and optimization metrics, such as area, throughput and latency. Function evalu ..."
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implement over 2000 placed-and-routed FPGA designs, resulting in over 100 million Application-Specific Integrated Circuit (ASIC) equivalent gates. We provide optimal function evaluation results for range and precision combinations between 8 and 48 bits. Index Terms — Computer arithmetic, elementary function
IEEE TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS 1 Using Gaussian
"... process with test rejection to detect T-cell epitopes in pathogen genomes ..."
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process with test rejection to detect T-cell epitopes in pathogen genomes
IEEE TRANSACTIONS ON COMPUTERS, VOL. *, NO. *, * * 1 The Reliability Wall for Exascale
"... Abstract—Reliability is a key challenge to be understood to turn the vision of exascale supercomputing into reality. Inevitably, large-scale supercomputing systems, especially those at the peta/exascale levels, must tolerate failures, by incorporating faulttolerance mechanisms to improve their relia ..."
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Abstract—Reliability is a key challenge to be understood to turn the vision of exascale supercomputing into reality. Inevitably, large-scale supercomputing systems, especially those at the peta/exascale levels, must tolerate failures, by incorporating faulttolerance mechanisms to improve their reliability and availability. As the benefits of fault-tolerance mechanisms rarely come without associated time and/or capital costs, reliability will limit the scalability of parallel applications. This paper introduces for the first time the concept of “Reliability Wall ” to highlight the significance of achieving scalable performance in peta/exascale supercomputing with fault tolerance. We quantify the effects of reliability on scalability, by proposing a reliability speedup, defining quantitatively the reliability wall, giving an existence theorem for the reliability wall, and categorizing a given system according to the time overhead incurred by fault tolerance. We also generalize these results into a general reliability speedup/wall framework by considering not only speedup but also costup. We analyze and extrapolate the existence of the reliability wall using two representative supercomputers, Intrepid and ASCI White, both employing checkpointing for fault tolerance, and have also studied the general reliability wall using Intrepid. These case studies provide insights on how to mitigate reliability-wall effects in system design and through hardware/software optimizations in peta/exascale supercomputing.
IEEE TRANSACTIONS ON COMPUTATIONAL INTELLIGENCE AND AI IN GAMES 1 Procedural generation of dungeons
"... Abstract—The use of procedural content generation (PCG) techniques in game development has been mostly restricted to very specific types of game elements. PCG has been seldom deployed for generating entire game levels, a notable exception to this being dungeons, a specific type of game levels often ..."
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Abstract—The use of procedural content generation (PCG) techniques in game development has been mostly restricted to very specific types of game elements. PCG has been seldom deployed for generating entire game levels, a notable exception to this being dungeons, a specific type of game levels often encountered in adventure and role playing games. Due to their peculiar combination of pace, gameplay and game spaces, dungeon levels are among the most suited to showcase the benefits of PCG. This article surveys research on procedural methods to generate dungeon game levels. We summarize common practices, discuss pros and cons of different approaches, and identify a few promising challenges ahead. In general, what current procedural dungeon generation methods are missing is not performance, but more powerful, accurate and richer control over the generation process. Recent research results seem to indicate that gameplay-related criteria can provide such high-level control. However, this area is still in its infancy, and many research challenges are still lying ahead, e.g. improving the intuitiveness and accessibility of such methods for designers. We also observe that more research is needed into generic mechanisms for automating the generation of the actual dungeon geometric models. We conclude that the foundations for enabling gameplay-based control of dungeon-level generation are worth being researched, and that its promising results may be instrumental in bringing PCG into mainstream game development. Index Terms—Procedural content generation, procedural level generation, role playing games, gameplay semantics. I.
IEEE TRANSACTIONS ON COMPUTERS 1 Elliptic Curve Based Security Processor for RFID
"... Abstract — RFID (Radio Frequency IDentification) tags need to include security functions, yet at the same time their resources are extremely limited. Moreover, to provide privacy, authentication and protection against tracking of RFID tags without loosing the system scalability, a public-key based a ..."
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Abstract — RFID (Radio Frequency IDentification) tags need to include security functions, yet at the same time their resources are extremely limited. Moreover, to provide privacy, authentication and protection against tracking of RFID tags without loosing the system scalability, a public-key based approach is inevitable. In this paper, we present an architecture of a state-of-the-art pro-cessor for RFID tags with an Elliptic Curve (EC) processor over GF(2163). It shows the plausibility of meeting both security and efficiency requirements even in a passive RFID tag. The proposed processor is able to perform EC scalar multiplications as well as general modular arithmetic (additions and multiplications) which are needed for the cryptographic protocols. As we work with large numbers, the register file is the most critical component in the architecture. By combining several techniques, we are able to reduce the number of registers from 9 to 6 in the EC processor. To obtain an efficient modulo arithmetic, we introduce a redundant modular operation. Moreover, the proposed architecture can support multiple cryptographic protocols. The synthesis results with a 0.13 µm CMOS technology show that the gate area of the most compact version is 12.5 Kgates.
Not for Citation. Submitted to IEEE Transactions on Computational Intelligence and AI in Games; Comments welcome
"... Abstract—I describe a procedural animation system that uses techniques from behavior-based robot control, combined with a minimalist physical simulation, to produce believable character motions in a dynamic world. Although less realistic than motion capture or full biomechanical simulation, the syst ..."
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Abstract—I describe a procedural animation system that uses techniques from behavior-based robot control, combined with a minimalist physical simulation, to produce believable character motions in a dynamic world. Although less realistic than motion capture or full biomechanical simulation, the system produces compelling, responsive character behavior. It is also fast, supports believable physical interactions between characters such as hugging, and makes it easy to author new behaviors. Index Terms—Virtual characters, interactive narrative, procedural animation. I.
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