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3d-stacked memory-side acceleration: Accelerator and system design

by Qi Guo, Nikolaos Alachiotis, Berkin Akin, Fazle Sadi, Guanglin Xu, Tze Meng Low, Larry Pileggi, James C. Hoe, Franz Franchetti - in In the Workshop on Near-Data Processing (WoNDP) (Held in conjunction with MICRO-47 , 2014
"... Abstract—Specialized hardware acceleration is an effective technique to mitigate the dark silicon problems. A challenge in designing on-chip hardware accelerators for data-intensive applications is how to efficiently transfer data between the memory hierarchy and the accelerators. Although the Proce ..."
Abstract - Cited by 1 (1 self) - Add to MetaCart
, thus leading to the concept of the 3D-stacked Memory-Side Accelerator (MSA). In this paper, we initially present the overall architecture of the 3D-stacked MSA, which relies on a configurable array of domain-specific accelerators. Thereafter, we describe a full-system prototype that is built upon a

Composable memory transactions

by Tim Harris, Mark Plesko, Avraham Shinnar, David Tarditi - In Symposium on Principles and Practice of Parallel Programming (PPoPP , 2005
"... Atomic blocks allow programmers to delimit sections of code as ‘atomic’, leaving the language’s implementation to enforce atomicity. Existing work has shown how to implement atomic blocks over word-based transactional memory that provides scalable multiprocessor performance without requiring changes ..."
Abstract - Cited by 506 (42 self) - Add to MetaCart
repeatedly in an atomic block), (3) we use runtime filtering to detect duplicate log entries that are missed statically, and (4) we present a series of GC-time techniques to compact the logs generated by long-running atomic blocks. Our implementation supports short-running scalable concurrent benchmarks

Run-time Reconfigurable Hardware

by Yang Qu, Vtt Publications, Yang Qu , 2007
"... System-level design and configuration management for run-time reconfigurable devices IIR ..."
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System-level design and configuration management for run-time reconfigurable devices IIR

TreadMarks: Distributed Shared Memory on Standard Workstations and Operating Systems

by Pete Keleher , Alan L. Cox, Sandhya Dwarkadas, Willy Zwaenepoel - IN PROCEEDINGS OF THE 1994 WINTER USENIX CONFERENCE , 1994
"... TreadMarks is a distributed shared memory (DSM) system for standard Unix systems such as SunOS and Ultrix. This paper presents a performance evaluation of TreadMarks running on Ultrix using DECstation-5000/240's that are connected by a 100-Mbps switch-based ATM LAN and a 10-Mbps Ethernet. Ou ..."
Abstract - Cited by 527 (17 self) - Add to MetaCart
TreadMarks is a distributed shared memory (DSM) system for standard Unix systems such as SunOS and Ultrix. This paper presents a performance evaluation of TreadMarks running on Ultrix using DECstation-5000/240's that are connected by a 100-Mbps switch-based ATM LAN and a 10-Mbps Ethernet

Managing Energy and Server Resources in Hosting Centers

by Jeffrey S. Chase, Darrell C. Anderson, Prachi N. Thakar, Amin M. Vahdat - In Proceedings of the 18th ACM Symposium on Operating System Principles (SOSP , 2001
"... Interact hosting centers serve multiple service sites from a common hardware base. This paper presents the design and implementation of an architecture for resource management in a hosting center op-erating system, with an emphasis on energy as a driving resource management issue for large server cl ..."
Abstract - Cited by 558 (37 self) - Add to MetaCart
Interact hosting centers serve multiple service sites from a common hardware base. This paper presents the design and implementation of an architecture for resource management in a hosting center op-erating system, with an emphasis on energy as a driving resource management issue for large server

Garp: A MIPS Processor with a Reconfigurable Coprocessor

by John R. Hauser , John Wawrzynek , 1997
"... Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presen ..."
Abstract - Cited by 402 (6 self) - Add to MetaCart
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture

FASTER Run-time Reconfiguration Management

by Cătălin Bogdan Ciobanu, Dionisios N. Pnevmatikatos, Kyprianos D. Papadimitriou, Georgi N. Gaydadjiev
"... The FASTER project Run-Time System Manager offloads programmers from low-level operations by performing task placement, scheduling, and dynamic FPGA reconfiguration. It also manages device fragmentation, configuration caching, pre-fetching and reuse, bitstream compression, and optimizes the system t ..."
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The FASTER project Run-Time System Manager offloads programmers from low-level operations by performing task placement, scheduling, and dynamic FPGA reconfiguration. It also manages device fragmentation, configuration caching, pre-fetching and reuse, bitstream compression, and optimizes the system

Fine-grained Mobility in the Emerald System

by Eric Jul, Henry Levy, Norman Hutchinson, Andrew Black - ACM Transactions on Computer Systems , 1988
"... Emerald is an object-based language and system designed for the construction of distributed programs. An explicit goal of Emerald is support for object mobility; objects in Emerald can freely move within the system to take advantage of distribution and dynamically changing environments. We say that ..."
Abstract - Cited by 548 (24 self) - Add to MetaCart
and run-time mechanisms that support mobility, and techniques for implementing mobility that do not degrade the performance of local operations. Performance measurements of the current implementation are included.

JFlow: Practical Mostly-Static Information Flow Control

by Andrew C. Myers - In Proc. 26th ACM Symp. on Principles of Programming Languages (POPL , 1999
"... A promising technique for protecting privacy and integrity of sensitive data is to statically check information flow within programs that manipulate the data. While previous work has proposed programming language extensions to allow this static checking, the resulting languages are too restrictive f ..."
Abstract - Cited by 579 (32 self) - Add to MetaCart
models: a decentralized label model, label polymorphism, run-time label checking, and automatic label inference. JFlow also supports many language features that have never been integrated successfully with static information flow control, including objects, subclassing, dynamic type tests, access control

Valgrind: A framework for heavyweight dynamic binary instrumentation

by Nicholas Nethercote, Julian Seward - In Proceedings of the 2007 Programming Language Design and Implementation Conference , 2007
"... Dynamic binary instrumentation (DBI) frameworks make it easy to build dynamic binary analysis (DBA) tools such as checkers and profilers. Much of the focus on DBI frameworks has been on performance; little attention has been paid to their capabilities. As a result, we believe the potential of DBI ha ..."
Abstract - Cited by 545 (5 self) - Add to MetaCart
register and memory value with another value that describes it. This support accounts for several crucial design features that distinguish Valgrind from other DBI frameworks. Because of these features, lightweight tools built with Valgrind run comparatively slowly, but Valgrind can be used to build more
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