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High-Throughput LDPC decoders

by Mohammad M. Mansour, Naresh R. Shanbhag, Senior Member - IEEE Trans. on Very Large Scale Integration Systems , 2003
"... Abstract—A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design—namely LDPC code design, de ..."
Abstract - Cited by 107 (1 self) - Add to MetaCart
Abstract—A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design—namely LDPC code design

Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM

by Youn Sung Park, Student Member, David Blaauw, Dennis Sylvester, Zhengya Zhang
"... Abstract—The majority of the power consumption of a high-throughput LDPC decoder is spent on memory. Unlike in a gen-eral-purpose processor, the memory access in an LDPC decoder is deterministic and the access window is short. We take advantage of the unique memory access characteristic to design a ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
Abstract—The majority of the power consumption of a high-throughput LDPC decoder is spent on memory. Unlike in a gen-eral-purpose processor, the memory access in an LDPC decoder is deterministic and the access window is short. We take advantage of the unique memory access characteristic to design a

Design of a High-Throughput Low-Power IS95 Viterbi Decoder

by Xun Liu, Marios C. Papaefthymiou - In DAC , 2002
"... The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption. In this paper, we propose a data- ..."
Abstract - Cited by 3 (0 self) - Add to MetaCart
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption. In this paper, we propose a data

High Throughput and Low Power Enhancements for LDPC Decoders

by Erick Amador, Renaud Pacalet, Vincent Rezard
"... Abstract—Modern VLSI decoders for low-density parity-check (LDPC) codes require high throughput performance while achieving high energy efficiency on the smallest possible foot-print. In this paper, we present two optimizations to enhance the throughput and reduce the power consumption for these dec ..."
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Abstract—Modern VLSI decoders for low-density parity-check (LDPC) codes require high throughput performance while achieving high energy efficiency on the smallest possible foot-print. In this paper, we present two optimizations to enhance the throughput and reduce the power consumption

Split-Row: A reduced complexity, high throughput LDPC decoder architecture

by T. Mohsenin, B. M. Baas - in ICCD , 2006
"... Abstract — A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row method makes column processing parallelism easier to exploit, doubles available row processor parallelism, and sig ..."
Abstract - Cited by 18 (9 self) - Add to MetaCart
Abstract — A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row method makes column processing parallelism easier to exploit, doubles available row processor parallelism

Power reduction techniques for LDPC decoders

by Ahmad Darabiha, Student Member, Anthony Chan Carusone, Frank R. Kschischang - IEEE J. Solid-State Circuits , 2008
"... Abstract—This paper investigates VLSI architectures for low-density parity-check (LDPC) decoders amenable to low- voltage and low-power operation. First, a highly-parallel decoder archi-tecture with low routing overhead is described. Second, we propose an efficient method to detect early convergence ..."
Abstract - Cited by 17 (0 self) - Add to MetaCart
Abstract—This paper investigates VLSI architectures for low-density parity-check (LDPC) decoders amenable to low- voltage and low-power operation. First, a highly-parallel decoder archi-tecture with low routing overhead is described. Second, we propose an efficient method to detect early

ABSTRACT Compiler-Based Register Name Adjustment for Low-Power Embedded Processors

by Peter Petrov
"... We present an algorithm for compiler-driven register name adjustment with the main goal of power minimization on instruction fetch and register file access. In most instruction set architecture (ISA) designs, the register fields reside in fixed positions within the instruction encoding, hence formin ..."
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forming streams of indices on the instruction bus and to the register file address decoder. The number of bit transitions in these streams greatly determines the power consumption on the address bus and the register file decoder. While general-purpose registers are semantically indistinguishable and hence

Compiler-Based Register Name Adjustment for Low-Power Embedded Processors

by Peter Petrov, et al. , 2003
"... We present an algorithm for compiler-driven register name adjustment with the main goal of power minimization on instruction fetch and register file access. In most instruction set architecture (ISA) designs, the register fields reside in fixed positions within the instruction encoding, hence formin ..."
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forming streams of indices on the instruction bus and to the register file address decoder. The number of bit transitions in these streams greatly determines the power consumption on the address bus and the register file decoder. While general-purpose registers are semantically indistinguishable and hence

Efficient DSP implementation of an LDPC decoder

by Gottfried Lechner, Jossy Sayir - in Proc. International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004 , 2004
"... We present a high performance implementation of a belief propagation decoder for decoding low-density parity-check (LDPC) codes on a fixed point digital signal processor. A simplified decoding algorithm was used and a stopping criteria for the iterative decoder was implemented to reduce the average ..."
Abstract - Cited by 8 (1 self) - Add to MetaCart
We present a high performance implementation of a belief propagation decoder for decoding low-density parity-check (LDPC) codes on a fixed point digital signal processor. A simplified decoding algorithm was used and a stopping criteria for the iterative decoder was implemented to reduce the average

2011 IEEE Information Theory Workshop Gigabit Rate Low-Power LDPC Decoder 1 Samsung Electronics

by Eran Pisek, Dinesh Rajan, Joseph Clevel
"... Abstract — LDPC codes are becoming popular in next generation high throughput wireless standards since they can provide a level of parallelism with sufficient performance to support the high gigabit rate. In this paper, we propose a new method for LDPC decoding called Parallel Processing Layered (PP ..."
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Abstract — LDPC codes are becoming popular in next generation high throughput wireless standards since they can provide a level of parallelism with sufficient performance to support the high gigabit rate. In this paper, we propose a new method for LDPC decoding called Parallel Processing Layered
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