### Table 2: Minimum Power Dissipation.

"... In PAGE 14: ... Thus, with no increase of the corresponding area, power reduction can be achieved. The minimum power dissipation that corresponds to each row of Table 1 is shown in Table2 . It can be noticed that the power reduction it could be more than 20 % ( n =7, R =0.... In PAGE 26: ...LIST OF TABLES Table 1 : Mean Power Reduction. Table2 : Minimum Power Dissipation. LIST OF FIGURES Figure 1.... ..."

### TABLE IV. MINIMUM POWER SOLUTIONS FOR DCT

### Table II: Minimum Power Dissipation for AVERAGE =100.

### TABLE IV. MINIMUM POWER SOLUTIONS FOR DCT

### Table 2: The delay and power before and after wire-sizing. The gains are measured by the initial values divided by the optimized values. Initial(w = 1 m) ClockTune(wm = 0:3 m;wM = 3 m; wbm = 1;wbM = 10;p = q = r = 64) Input delay load minimum-delay solution minimum-power solution CPU

"... In PAGE 5: ... The numbers of samples used in the min-ZSBWS problem are p = q = r = 64. Table2 shows the minimum-delay and minimum-power solutions for the min-ZSWS problem. If the initial routing does not use the minimum wire-width, then both the delay and power can be lowered by performing wire-sizing.... ..."

### Table 6: Minimum power from deterministic sizing at an intermediate coe cient of yield K = 2:39 (all random variables are set to K ). Circuit Power (mW)

2005

"... In PAGE 5: ... For a speci c value, K = 2:39, we compute minimum power from deterministic sizing. These results for the ISCAS-85 circuits are shown in Table6 . The optimal power numbers... ..."

Cited by 1

### Table 3: Minimum power obtained by deterministic ( = 3) and statistical approaches ( = 99:8% tar- get yield) for di erent timing targets (deterministic sizing / statistical sizing).

2005

"... In PAGE 4: ... We use Tmin as the timing target for the deterministic and statisti- cal sizing problems. Table3 presents the power savings obtained from statisti- cal sizing. The Tmin for each circuit is presented in column 2.... In PAGE 6: ... Even though the circuit was optimized for power under the constraint that circuit delay is less than Tmin, the worst-case deterministic sizing gives a much tighter clock period. This ensures a 100% yield, but at the expense of increased power (from Table3 , power is 0:511mW). 0.... ..."

Cited by 1

### Table 3. Summary of Results (Install high-efficiency compressed-air system)

### Table 2: Comparison of the power delay product minima obtained for a two stage array, to the values obtained by sizing the 2nd stage for q min or at Tlimit. For illustration we represent in Table 2 the variation, with CIN2, of the power-delay product (equ.18) for a configuration of 2 real inverters. The load has been imposed equal to 10 CIN1 and the configuration ratio k=1. As shown, depending on the parasitic content of the array implementation, tapering factors for minimum power delay implementations exhibit a small variation with respect to the parasitic load. Alternatives, with explicit solutions, allow interesting trade offs between speed and power with a few penalty on the power delay product. As shown, an explicit sizing at Tlimit constitutes a good solution for low power implementations.

### Table 2: Optimization results as a function of the number of stages. The minimum power design consists of 3 stages. The 4 stage design exhibits lower bandwidth and gain performances to minimize noise, while 5 stages have definitely larger noise and power consumption.

2004

Cited by 2