Results 1 - 10 of 38

An Efficient Hardware Architecture for H.264 Transform and Quantization Algorithms

by Logashanmugam E , Ramachandran
"... Abstract -In this paper, we present a high performance, low cost and low power hardware architecture for real-time implementation of forward transform and quantization and inverse transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard. The proposed hardware implem ..."
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Abstract -In this paper, we present a high performance, low cost and low power hardware architecture for real-time implementation of forward transform and quantization and inverse transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard. The proposed hardware

AN EFFICIENT H.264 INTRA FRAME CODER HARDWARE DESIGN

by Esra Şahi̇n, Assist Prof, Dr. İlker Hamzaoğlu, Assist Prof, Dr. Ayhan Bozkurt, Esra Şahin, Esra Şahin , 2006
"... H.264 / MPEG-4 Part 10, a recently developed international standard for video compression, offers significantly better video compression efficiency than previous international standards. Since it is impossible to implement a real-time H.264 video coder using a state-of-the-art embedded processor alo ..."
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alone, in this thesis, we developed an efficient FPGA-based H.264 intra frame coder hardware for real-time portable applications targeting level 2.0 of baseline profile. We first designed a high performance and low cost hardware architecture for realtime implementation of entropy coding algorithms

Joint prediction algorithm and architecture for stereo video hybrid coding systems

by Li-fu Ding, Shao-yi Chien, Liang-gee Chen - IEEE Trans
"... Abstract—3-D video will be the most prominent video technology in the next generation. Among the 3-D video technologies, stereo video systems are considered to be realized first in the near future. Stereo video systems require double bandwidth and more than twice the computational complexity relativ ..."
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-matching algorithm, only 11.5 % on-chip SRAM and 3.3 % processing elements are needed with a tiny PSNR drop, making it area-efficient while maintaining high stereo video quality and processing capability. Index Terms—Hardware architecture, joint prediction algorithm (JPA), stereo video coding, 3-D video. I.

A HIGHLY DATA REUSABLE AND STANDARD-COMPLIANT MOTION ESTIMATION HARDWARE ARCHITECTURE

by Xing Wen , Oscar C Au , Jiang Xu , Lu Fang , Run Cha , Jiali Li
"... ABSTRACT Motion Estimation (ME) is the most computationally intensive part in the whole video compression process. The ME algorithms can be divided into full search ME (FS) and fast ME (FME). The FS is not suitable for high definition (HD) frame size videos because its relevant high computation loa ..."
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vector field (MVF) coherence and rate-distortion (RD) cost which have significant impact to the coding efficiency. In this paper, we propose a hardware friendly ME algorithm and corresponding highly data reusable hardware architecture. Simulation results show that the proposed ME algorithm performs

An efficient hardware implementation for motion estimation of AVC standard

by Lei Deng, Wen Gao, Ming Zeng Hu, Zhen Zhou Ji - IEEE Trans. Consumer Electron , 2005
"... Abstract — In the advanced video coding standard (AVC), motion estimation adopts many new features such as variable block size searching, multiple reference frames, motion vector prediction, etc, for enhancing the coding performance. However, the high data dependence and high computation requirement ..."
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Abstract — In the advanced video coding standard (AVC), motion estimation adopts many new features such as variable block size searching, multiple reference frames, motion vector prediction, etc, for enhancing the coding performance. However, the high data dependence and high computation

High-speed Motion Estimation Architecture for Real-time Video Transmission

by Sumeer Goel, Yasser Ismail, Magdy Bayoumi , 2010
"... Motion estimation (ME) process consumes up to 70 % of the total encoding time of video transmission. Because it has a high coding efficiency and it is very scalable, the full search (FS) algorithm is considered to be the most popular ME algorithm. However, the main drawback of the FS algorithm is th ..."
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Motion estimation (ME) process consumes up to 70 % of the total encoding time of video transmission. Because it has a high coding efficiency and it is very scalable, the full search (FS) algorithm is considered to be the most popular ME algorithm. However, the main drawback of the FS algorithm

doi:10.1093/comjnl/bxr034 High-speed Motion Estimation Architecture for Real-time Video Transmission

by Sumeer Goel, Yasser Ismail, Magdy Bayoumi , 2010
"... Motion estimation (ME) process consumes up to 70 % of the total encoding time of video transmission. Because it has a high coding efficiency and it is very scalable, the full search (FS) algorithm is considered to be the most popular ME algorithm. However, the main drawback of the FS algorithm is th ..."
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Motion estimation (ME) process consumes up to 70 % of the total encoding time of video transmission. Because it has a high coding efficiency and it is very scalable, the full search (FS) algorithm is considered to be the most popular ME algorithm. However, the main drawback of the FS algorithm

LSI design for MPEG-4 coding system

by Yung-chi Chang, Wei-min Chao, Liang-gee Chen - in Proceedings of 47th Midwest Symposium on Circuits and Systems (MWSCAS ’04 , 2004
"... video coding. We adopt platform-based architecture with an em-bedded RISC core and efficient memory organization. A fast mo-tion estimator architecture supporting predictive diamond search and spiral full search with halfway termination is implemented to make good compromise between compression perf ..."
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performance and design cost. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. With high de-gree of optimization in both algorithm and architecture levels, a cost-efficient video encoder LSI is implemented. It consumes 256.8mW at 40MHz and achieves real

Parallel Modelling Paradigm in Multimedia Applications: Mapping and Scheduling onto a Multi-Processor System-on-Chip Platform

by Nuria Pazos, Paolo Ienne, Yusuf Leblebici, Alexander Maxiaguine - In Proc. of the International Global Signal Processing Conference , 2004
"... Multi-processor systems have appeared as a promising alternative to face the difficulties of creating even faster uni-processor systems using latest technologies. Emerging design paradigms such as Multiprocessor System-ona-Chip (MpSoC) offer high levels of performance and flexibility and at the same ..."
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and at the same time promise low-cost, reliable and power-efficient implementations. However, the design complexity of such systems have increased tremendously. One source of the complexity stems from highly parallel heterogeneous nature of the underlying hardware architecture, which poses many challenges

Ching-Yeh Chen, Yu-Han Chen, Chuan-Yung Tsai,

by Liang-gee Chen
"... The new H.264/AVC coding standard significantly outperforms previous video coding standards with many new coding tools. However, the high performance comes at a price. Its extraordinarily huge computational complexity and memory access requirement makes it difficult to design a hardwired codec for r ..."
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The new H.264/AVC coding standard significantly outperforms previous video coding standards with many new coding tools. However, the high performance comes at a price. Its extraordinarily huge computational complexity and memory access requirement makes it difficult to design a hardwired codec
Results 1 - 10 of 38