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173,417
Hierarchical GateLevel Verification of SpeedIndependent Circuits
 In Asynchronous Design Methodologies
, 1995
"... This paper presents a method for the verification of speedindependent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flipflops) of the circuit. Despite ..."
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Cited by 6 (3 self)
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This paper presents a method for the verification of speedindependent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flipflops) of the circuit. Despite
Sufficient Conditions for Correct GateLevel SpeedIndependent Circuits
 In Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems
, 1994
"... We describe sufficient conditions for the correctness of speedindependent asynchronous circuits. The circuit specifications considered are determinate, allowing input choice but not output choice (arbitration). The circuit implementations considered are networks of singleoutput basic gates. A circ ..."
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Cited by 7 (2 self)
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We describe sufficient conditions for the correctness of speedindependent asynchronous circuits. The circuit specifications considered are determinate, allowing input choice but not output choice (arbitration). The circuit implementations considered are networks of singleoutput basic gates. A
SIS: A System for Sequential Circuit Synthesis
, 1992
"... SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential inputoutput b ..."
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Cited by 514 (41 self)
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SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential input
Verification of SpeedIndependent DataPath
 In IEE ProceedingsComputers and Digital Techniques
, 1996
"... This paper demonstrates that verification techniques developed for relatively large, synchronous circuits can be applied to speedindependent, selftimed circuits. We introduce local formulas which provide a natural way to specify the input/output behaviour of datapath circuits. The validity of ..."
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of a local formula is independent of the order in which the operations occur in a speedindependent circuit. We demonstrate our approach with the verification of two designs: a FIFO, and a vector multiplier chip.
ComputerAided Synthesis And Verification Of GateLevel Timed Circuits
, 1995
"... In recent years, there has been a resurgence of interest in the design of asynchronous circuits due to their ability to eliminate clock skew problems, achieve average case performance, adapt to processing and environmental variations, provide component modularity, and lower system power requirement ..."
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Cited by 47 (21 self)
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In recent years, there has been a resurgence of interest in the design of asynchronous circuits due to their ability to eliminate clock skew problems, achieve average case performance, adapt to processing and environmental variations, provide component modularity, and lower system power
Conservative symbolic modelchecking of Petri nets for speedindependent circuit verification
, 1994
"... This paper presents a conservative symbolic modelchecking methodology for speedindependent circuits. The circuit specification is described by using Petri nets, which is the same formalism that several approaches use for synthesis. The technique is based on symbolic BDDbased reachability analysis, ..."
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Cited by 1 (0 self)
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conservative, although much more efficient. The applicability of these techniques has been proved by verifying the correctness and speedindependence of some benchmarks. 1 Introduction During these last few years, asynchronous circuits have gained interest due to their promising advantages, such us local
Characterizing Speedindependence of HighLevel Designs
 In Proceedings of the Symposium on Advanced Reserch in Asynchronous Cirsuits and Systems
, 1994
"... This paper characterizes the speedindependence of highlevel designs. The characterization is a condition on the design description ensuring that the behavior of the design is independent of the speeds of its components. The behavior of a circuit is modeled as a transition system, that allows data ..."
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This paper characterizes the speedindependence of highlevel designs. The characterization is a condition on the design description ensuring that the behavior of the design is independent of the speeds of its components. The behavior of a circuit is modeled as a transition system, that allows data
A theory of timed automata
, 1999
"... Model checking is emerging as a practical tool for automated debugging of complex reactive systems such as embedded controllers and network protocols (see [23] for a survey). Traditional techniques for model checking do not admit an explicit modeling of time, and are thus, unsuitable for analysis of ..."
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Cited by 2651 (32 self)
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using finitely many realvalued clock variables. Automated analysis of timed automata relies on the construction of a finite quotient of the infinite space of clock valuations. Over the years, the formalism has been extensively studied leading to many results establishing connections to circuits
Hiding Memory Elements in Induced Hierarchical Verification of SpeedIndependent Circuits
 in Proc. International Workshop on Logic Synthesis
, 1998
"... : The goal of induced hierarchical verification techniques is to automatically create hierarchy in an originally flat circuit in order to decompose the verification problem (i.e., checking hazardfreedom and conformance to a specification) into that of verifying a set of smaller subcircuits. Existi ..."
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Cited by 3 (1 self)
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. Existing induced hierarchical verification techniques for speedindependent circuits are limited because the output of any memory element (e.g., Muller Celement) must be a subcircuit output (i.e., memory elements cannot be hidden). Consequently, these techniques have exponential complexity in the number
LowPower CMOS Digital Design
 JOURNAL OF SOLIDSTATE CIRCUITS. VOL 27, NO 4. APRIL 1992 413
, 1992
"... Motivated by emerging batteryoperated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for lowpower operation are shown which use the ..."
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Cited by 570 (20 self)
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Motivated by emerging batteryoperated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for lowpower operation are shown which use
Results 1  10
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173,417