Tools
Sorted by:
Try your query at:
 |
 |
 |
 |
 |
 |
Results 1 - 10
of
175
Hardware and a Tool Chain for ADRES
"... Abstract. Until recently, only a compiler and a high-level simulator of the reconfigurable architecture ADRES existed. This paper focuses on the problems that needed to be solved when moving from a software-only view on the architecture to a real hardware implementation, as well as on the verificati ..."
Abstract
- Add to MetaCart
Abstract. Until recently, only a compiler and a high-level simulator of the reconfigurable architecture ADRES existed. This paper focuses on the problems that needed to be solved when moving from a software-only view on the architecture to a real hardware implementation, as well
Automatic hardware-efficient SoC integration by QoS network on chip
- In ICECS
, 2004
"... Abstract — Efficient module integration in Systems on Chip (SoC) is a great challenge. We present a novel automated Network on Chip (NoC) centric integration method for large and complex SoCs. A Quality of Service NoC (QNoC) architecture and its design considerations are presented. Then we describe ..."
Abstract
-
Cited by 12 (0 self)
- Add to MetaCart
a chain of design automation tools that allows fast and hardware-efficient SoC integration using the QNoC paradigm. The tool-chain receives a list of system modules and their inter-module communication requirements and results in a complete system hardware and verification models for faster So
Hardware/Software Design Space Exploration for a Reconfigurable Processor
, 2003
"... This paper describes an approach to hardware /software design space exploration for reconfigurable processors. The existing compiler tool-chain, because of the user-definable instructions, needs to be extended in order to offer developers an easy way to explore design space. Such extension often is ..."
Abstract
-
Cited by 12 (0 self)
- Add to MetaCart
This paper describes an approach to hardware /software design space exploration for reconfigurable processors. The existing compiler tool-chain, because of the user-definable instructions, needs to be extended in order to offer developers an easy way to explore design space. Such extension often
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard
- in Proc. of the IEEE Int. Test Conf. (ITC), 2004
, 2004
"... Scan based test is a double edged sword. On one hand, it is a powerful test technique. On the other hand, it is an equally powerful attack tool. In this paper we show that scan chains can be used as a side channel to recover secret keys from a hardware implementation of the Data Encryption Standard ..."
Abstract
-
Cited by 30 (2 self)
- Add to MetaCart
Scan based test is a double edged sword. On one hand, it is a powerful test technique. On the other hand, it is an equally powerful attack tool. In this paper we show that scan chains can be used as a side channel to recover secret keys from a hardware implementation of the Data Encryption Standard
Towards Creating Flexible Tool Chains for the Design and Analysis of Multi-Core Systems ∗†
"... Abstract: With the ever increasing complexity of today’s embedded systems, also the complexity of the design and development processes tends to grow. Experts from different domains and/or organizations work on different aspects of a product. Tool support is necessary for these activities, like desig ..."
Abstract
-
Cited by 2 (0 self)
- Add to MetaCart
design of hardware and software, requirements engineering and verification. While an increasing number of tools is available, these tools are usually not integrated. Hence, it is difficult to establish a traceability between data created by these tools and to access data created by a particular tool from
Automated Generation of Hardware Accelerators From Standard C
"... Methodologies for synthesis of stand-alone hardware modules from C/C++-based languages have been gaining adoption for embedded system design as an essential means to stay ahead of increasing performance, complexity, and time-to-market demands. However, using C to generate stand-alone blocks does not ..."
Abstract
- Add to MetaCart
not allow for truly seamless unification of embedded software and hardware development flows. This paper describes a methodology for generating hardware accelerator modules that are tightly coupled with a soft RISC CPU, its tool chain, and its memory system. This coupling allows for several significant
Optical Hardware Tradeoffs for All Optical Multicast
, 2002
"... All Optical WDM Networks are fast becoming the natural choice for future backbones and in order to meet the exponentially increasing traffic demands, it would be beneficial to support all optical multicast. One way to support multicast is to provide optical splitters at various switching nodes along ..."
Abstract
- Add to MetaCart
simulation tool from Virtual Photonics was used to simulate a variety of multicast networks taking into account relevant Nonlinear effects such as chromatic dispersion, four wave mixing, stimulated Raman scattering and all phenomena commonly encountered in Cascaded EDFA chains such as Accumulated Spontaneous
High-Speed Hardware Implementations of BLAKE, Blue Midnight Wish, CubeHash,
, 2009
"... Abstract. In this paper we describe our high-speed hardware implementations of the 14 candidates of the second evaluation round of the SHA-3 hash function competition. We synthesized all implementations using a uniform tool chain, standard-cell library, target technology, and optimization heuristic. ..."
Abstract
-
Cited by 6 (0 self)
- Add to MetaCart
Abstract. In this paper we describe our high-speed hardware implementations of the 14 candidates of the second evaluation round of the SHA-3 hash function competition. We synthesized all implementations using a uniform tool chain, standard-cell library, target technology, and optimization heuristic
MDABased Development in the DECOS Integrated Architecture – Modeling the Hardware Platform
- Proc. of the 9th IEEE Int. Symp. on Object and ComponentOriented Real-Time Distribued Computing (ISORC
, 2006
"... Reduced time–to–market in spite of increasing the system’s functionality, reuse of software on different hardware platforms, and the demand for performing validation activities earlier in the development phase raise the need for revising the state–of–the–art development methodologies for distributed ..."
Abstract
-
Cited by 4 (1 self)
- Add to MetaCart
of the targeted hardware platform. In this paper we introduce a meta-model for capturing the resources of hardware platforms realizing the DECOS architecture, which is an integrated time-triggered architecture aimed at the development of distributed embedded systems. Furthermore, we present a tool chain based
Hardware Mechanism and Performance Evaluation of Hierarchical Page-Based Memory Bus Protection
"... Abstract—SecBus project aims at building a two-level pagebased memory bus protection platform. A trusted Operating System (OS) dynamically manages security contexts for memory pages. Via such contexts, an independent hardware module is driven to execute cryptographic protections. The fact that both ..."
Abstract
- Add to MetaCart
processor and software tool chain are not modified strengthens platform realizability and market acceptability. This paper presents SecBus hardware mechanism. Performance improvement is sustained by such optimization measures as usage of multiple caches, incoherent-Hash-Tree management and speculative
Results 1 - 10
of
175
