Results 1 - 10 of 1,468

A theory of timed automata

by Rajeev Alur , 1999
"... Model checking is emerging as a practical tool for automated debugging of complex reactive systems such as embedded controllers and network protocols (see [23] for a survey). Traditional techniques for model checking do not admit an explicit modeling of time, and are thus, unsuitable for analysis of ..."
Abstract - Cited by 2651 (32 self) - Add to MetaCart
of real-time systems whose correctness depends on relative magnitudes of different delays. Consequently, timed automata [7] were introduced as a formal notation to model the behavior of real-time systems. Its definition provides a simple way to annotate state-transition graphs with timing constraints

UPPAAL in a Nutshell

by Kim G. Larsen, Paul Pettersson, Wang Yi , 1997
"... . This paper presents the overall structure, the design criteria, and the main features of the tool box Uppaal. It gives a detailed user guide which describes how to use the various tools of Uppaal version 2.02 to construct abstract models of a real-time system, to simulate its dynamical behavior, ..."
Abstract - Cited by 662 (51 self) - Add to MetaCart
. This paper presents the overall structure, the design criteria, and the main features of the tool box Uppaal. It gives a detailed user guide which describes how to use the various tools of Uppaal version 2.02 to construct abstract models of a real-time system, to simulate its dynamical behavior

Tropos: An Agent-Oriented Software Development Methodology

by Paolo Bresciani, Paolo Giorgini, Fausto Giunchiglia, John Mylopoulos, Anna Perini , 2003
"... Our goal in this paper is to introduce and motivate a methodology, called Tropos, for building agent oriented software systems. Tropos is based on two key ideas. First, the notion of agent and all related mentalistic notions (for instance goals and plans) are used in all phases of software develop ..."
Abstract - Cited by 461 (91 self) - Add to MetaCart
and human agents. The methodology is illustrated with the help of a case study. The Tropos language for conceptual modeling is formalized in a metamodel described with a set of UML class diagrams.

Petri Nets Based Approach for Modular Verification of SysML Requirements on Activity Diagrams

by Messaoud Rahim, Malika Boukala-ioualalen, Ahmed Hammad
"... Abstract. The validation of SysML specifications needs a complete process for extracting, formalizing and verifying SysML requirements. Within an overall approach which considers an automatic verification of SysML designs by translating both requirement and behavioral diagrams, this paper proposes a ..."
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-to-model transformation to automatically derive from SysML activities a modular Petri net, then SysML require-ments are formalized and verified using the derived Petri net modules. A case study is presented to demonstrate the effectiveness of the proposed approach.

Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities”. Workshop

by Marcello Mura, Amrit Panda, Mauro Prevostini , 2008
"... In this paper two well known UML profiles, namely SysML and MARTE are closely examined and compared. Both profiles are well suited for the description of embed-ded systems, although focusing on different aspects and can therefore be considered as complementary. While SysML targets system engineering ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
In this paper two well known UML profiles, namely SysML and MARTE are closely examined and compared. Both profiles are well suited for the description of embed-ded systems, although focusing on different aspects and can therefore be considered as complementary. While SysML targets system

TEPE: A SysML Language for Time-Constrained Property Modeling and Formal Verification

by Daniel Knorreck, Ludovic Apvrille
"... Using UML or SysML models in a verification-centric method requires a property expression language, a formal semantics, and a tool. The paper introduces TEPE, a graphical TEmporal Property Expression language based on SysML parametric diagrams. TEPE enriches the expressiveness of other common proper ..."
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Using UML or SysML models in a verification-centric method requires a property expression language, a formal semantics, and a tool. The paper introduces TEPE, a graphical TEmporal Property Expression language based on SysML parametric diagrams. TEPE enriches the expressiveness of other common

Combining SysML and Formals Methods for Safety Requirements Verification

by Gérard Morel , 2008
"... Nancy University) jointly with INRS (Institut National de Recherche et de Sécurité) deals with the verification of safety requirements for the design of complex control systems involving software, mechanical, or electrical components for industrial safety-critical applications such as power plant co ..."
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local properties of each component, but need to be studied through the emerging behaviour that issues from the interaction network. The main difficulties of this last verification are caused by the heterogeneity of the control components different technology domains that use proper design formalisms

A Formal Model of SysML Blocks using CSP for Assured Systems Engineering

by Jaco Jacobs , Andrew Simpson
"... Abstract. The Systems Modeling Language (SysML) is a semi-formal, visual modelling language used in the specification and design of systems. In this paper, we describe how Communicating Sequential Processes (CSP) and its associated refinement checker, Failures Divergences Refinement (FDR), gives ri ..."
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Abstract. The Systems Modeling Language (SysML) is a semi-formal, visual modelling language used in the specification and design of systems. In this paper, we describe how Communicating Sequential Processes (CSP) and its associated refinement checker, Failures Divergences Refinement (FDR), gives

1 Real-Time and Embedded System Verification Based on Formal Requirements

by B. Fontan, L. Apvrille, P. De Saqui-sannes, J. -p. Courtiat
"... TURTLE is a real-time UML profile supported by a toolkit which enables application of formal verification techniques to the analysis, design and deployment phases of systems design trajectory. This paper extends the TURTLE methodology with a requirement capture phase. SysML requirement diagrams are ..."
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TURTLE is a real-time UML profile supported by a toolkit which enables application of formal verification techniques to the analysis, design and deployment phases of systems design trajectory. This paper extends the TURTLE methodology with a requirement capture phase. SysML requirement diagrams

Formal Specification and Verification of a Real-Time Kernel

by Janusz Orski
"... The paper presents a case study of application of the VDM formal method to specification and verification of a simple real-time kernel. Specifications of selected external services of the kernel are presented. Then the verification methodology is introduced by demonstrating its basic steps in relati ..."
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The paper presents a case study of application of the VDM formal method to specification and verification of a simple real-time kernel. Specifications of selected external services of the kernel are presented. Then the verification methodology is introduced by demonstrating its basic steps
Results 1 - 10 of 1,468