### TABLE 2. Results of Formal Verification

1995

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### Table 3: Accuracy of signatures in formal verification

"... In PAGE 4: ... Here, signatures are used to find variable corre- spondences in pairs of Boolean functions prior to formal verifica- tion. The results are shown in Table3 . Even for large functions with many inputs few variable order aliases are observed.... ..."

### Table 1. Formal verification using BAN logic.

"... In PAGE 9: ... The deduction is quite lengthy and we omit it. We only show the idealized protocol and stepwise results in Table1 and omit the detailed discussion of the process. Step 1 is trivial.... In PAGE 9: ... Since that member has the control over the generation of the Bloom filter, P believes the Bloom filter (Postulate (3)). Based on these postulates, we can mechanically deduct and get the results as shown in Table1 . Moreover, the logic forces us to explicitly write down our assumptions to clarify our design goals.... ..."

### Table 6: Summary of human effort for the verification in MDGs and FormalCheck

"... In PAGE 28: ... On the other hand in FormalCheck, property checking on the implementation took about two man-weeks. Table6 gives a summary of human time taken to model and verify the design using both MDG and FormalCheck tools, where * means that FormalCheck does not need that modeling or verification phase. References [1] Bell Communication Research (BellCORE), SONET Transport Systems: Common Generic Criteria, GR-253-CORE, issue 2, December 1995.... ..."

### Table 1. Results from formal verification of safety with the necessary invariant constraints.

"... In PAGE 8: ... Safety was checked with the commutative correctness diagram used in [20][93][94][98]. Table1 shows the results from formal verification with the necessary invariant constraints. The old translation to CNF is without preserving the ITE-tree structure of equation arguments when eliminating equations, but using a disjunction of conjunctions.... ..."

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### Table 3: Acceptance of the circuit type by the formal verification tools.

"... In PAGE 6: ....1.4. Type of the circuit to be verified There are three types of the circuit to be verified: combinatorial, synchronous sequential, asynchronous sequential circuits. Almost all the examined tools can be applied to the verification of the combinatorial circuits except the symbolic model checker SMOCK (see Table3 ). Also most of the tools verify the synchronous sequential circuits.... ..."

### Table 1. FormalCheck statistics, initial verification

2002

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### TABLE IV SUMMARY OF FORMAL VERIFICATION FOR THE FORMULAS (21) AND (23)

2004

Cited by 1