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Table 2. wall clock times in seconds for I/O on the T3E.
1998
"... In PAGE 7: ... Strictly speaking, BUFFER OUT is not standard Fortran, so this approach is not portable. In Table2 we show the CPU time (column CPU) of our model without doing any I/O. For the I/O we show the minimum, average and maximum wall clock times.... In PAGE 7: ...From Table2 we see a signi cant di erence between minimum and maximum times. This is because we are dealing with shared physical devices.... ..."
Cited by 2
Table 1. Formal verification using BAN logic.
"... In PAGE 9: ... The deduction is quite lengthy and we omit it. We only show the idealized protocol and stepwise results in Table1 and omit the detailed discussion of the process. Step 1 is trivial.... In PAGE 9: ... Since that member has the control over the generation of the Bloom filter, P believes the Bloom filter (Postulate (3)). Based on these postulates, we can mechanically deduct and get the results as shown in Table1 . Moreover, the logic forces us to explicitly write down our assumptions to clarify our design goals.... ..."
Table 1. Verification Effort over Time. This table shows the cumulative amount of time spent on formal verification up to the nth week of the project. Times are in hours, recorded in 15 minute increments. Overhead indicates time spent on general overhead, such as setting up computers or installing software. Meetings indicates time spent in meetings; the time was multiplied by the number of peo- ple present if the meeting was for the formal verification project. Study indicates time spent study- ing the design. Model indicates time spent deciding how to model the design in Murphi. Code indicates time spent actually coding the Murphi model. Run indicates time spent waiting for verifi- cation jobs to run; it does not include the time taken by jobs left unattended. Most interesting verifi- cation traces and possible bugs occurred around the tenth week, as the basic model was completed and before lengthy runs were required. After the twentieth week, the project started winding down, with very large verification jobs left to run unsupervised on idle machines.
1997
"... In PAGE 5: ... Our experiences matched this pattern closely. We reached Milestone 1 in the second week of the project, after less than ten hours in total (See Table1 below.) had been spent on formal verification.... In PAGE 5: ... How much did the formal verification cost? Throughout the project, time spent on formal verification was carefully recorded. Table1 shows a week-by-week breakdown of cu- mulative time spent. The most striking feature of the data in Table 1 is that al- most no time was spent deciding how to model the problem.... In PAGE 5: ... Table 1 shows a week-by-week breakdown of cu- mulative time spent. The most striking feature of the data in Table1 is that al- most no time was spent deciding how to model the problem. This situation resulted mainly from our ability to reuse the results of previous work on verifying directory-based cache coherence protocols, as described in Section 4.... ..."
Cited by 2
Table 6: Summary of human effort for the verification in MDGs and FormalCheck
"... In PAGE 28: ... On the other hand in FormalCheck, property checking on the implementation took about two man-weeks. Table6 gives a summary of human time taken to model and verify the design using both MDG and FormalCheck tools, where * means that FormalCheck does not need that modeling or verification phase. References [1] Bell Communication Research (BellCORE), SONET Transport Systems: Common Generic Criteria, GR-253-CORE, issue 2, December 1995.... ..."
Table 3: Acceptance of the circuit type by the formal verification tools.
"... In PAGE 6: ....1.4. Type of the circuit to be verified There are three types of the circuit to be verified: combinatorial, synchronous sequential, asynchronous sequential circuits. Almost all the examined tools can be applied to the verification of the combinatorial circuits except the symbolic model checker SMOCK (see Table3 ). Also most of the tools verify the synchronous sequential circuits.... ..."
Table 1. Protocol elements for incremental UI updates
"... In PAGE 4: ...As shown in Table1 , XUP offers fine-grained updates to the UI model. For exam- ple, lt;xup:addUIElement gt; may be used to add a list item to a list box, and lt;xup:up- dateUIAttr gt; may be used to update the background color of a button.... In PAGE 6: ... In addition, since the client now maintains the UI state, the server-side application code no longer needs to regenerate screen / page every time. Through the protocol elements in Table1 , XUPClient allows application code on the server side to manipulate its client-side UI state. In this case, UI updates are mar- shaled through XUP protocol responses, and each response may contain multiple additions, removals, and updates of UI components and properties.... ..."
Table 2: Verification results of model checking on the abstracted model of TMRS using FormalCheck
Table 3: Verification results of model checking on the original model of TMRS using FormalCheck
Table 2: Verification results of model checking on the abstracted model of TMRS using FormalCheck
1999
Table 3: Verification results of model checking on the original model of TMRS using FormalCheck
1999
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