"... In PAGE 5: ... Therefore, the switching activities used for the estimation are derived from such streams. Table8 reports the total power consumptionresults. The power value of the dual T0 BI encoder is approximately one order of magnitude worse than the one of the T0 encoder for on-chip loads up to 0:4 pF, while for higher values the di#0Berence is re- duced.... ..."

"... In PAGE 5: ... Therefore, the switching activities used for the estimation are derived from such streams. Table8 reports the total power consumptionresults. The power value of the dual T0 BI encoder is approximately one order of magnitude worse than the one of the T0 encoder for on-chip loads up to 0:4 pF, while for higher values the di#0Berence is re- duced.... ..."

"... In PAGE 3: ....185(1GHz), 0.740(4GHz) Distribution of leakage power between router and links. From Table5 , it is evident that full-swing on-chip link drivers and wires consume substantial dynamic power, overwhelming that of the router core in 0.10 and 0.... ..."

"... In PAGE 4: ... We used Cacti to explore the partitioning necessary to minimize the access time of two different on-chip memories: TLBs and caches. The results are shown in Table1 , which displays the N parameters that produce the fastest ac- cess time for various organizations. Each N parameter is limited to a maximum value of eight to avoid unreasonable aspect ratios.... In PAGE 7: ... The resulting increase in access time may critically impact performance as we describe in Section 4. Therefore, in this paper we assume that we do not deviate from the speed-optimal partitioning of Table1 in applying this approach to on-chip memory structures. 3.... In PAGE 8: ...1 HARDWARE ORGANIZATION Figure 3 is an overall diagram of a 4-way set associative cache using selective cache ways. The wordlines of the data array are segmented either four or eight times according to the Cacti results of Table1 , creating four separate data way partitions. The bitlines of each data way may be segmented as well, although this is not shown in the diagram.... In PAGE 9: ...3% of a conventional cache. Our Cacti-based timing estimates indicate that for the cache organizations we have studied, segmenting the tag wordlines can in some cases result in a significant cache cycle time degradation relative to the optimal tag N parameters of Table1 . For example, Table 2 shows that the cycle time degradation incurred when the tag wordlines are segmented is roughly... In PAGE 10: ... Mem Level Organization L1 Icache 64KB, 4-way set assoc, 32B block, random, 1 cycle latency L1 Dcache 64KB, 4-way set assoc, selective cache ways, 2 ports, 32B block, random, 1 cycle latency L2 cache 512KB, 1MB, or 2MB, 4-way set assoc, 32B block, LRU, 15 cycle latency, 16 partitions main memory 16B bus width, 75 cycle initial latency, 2 cycles thereafter typically a critical path, especially for caches as large as those in this table, this degradation may result in an overall cycle time increase. For these reasons, we used the N parameters of Table1 and therefore only save energy in the data portion of the cache. However, the data portion comprises roughly 90% of the total energy dissipation for the cache organizations we have studied.... ..."

"... In PAGE 8: ... A detailed description of the models used was presented in [19, 20]. Table3 provides the energy consumption values of the used data memory modules. It can be easily seen that the total off-chip memory energy consumption (in J) is reduced around five times, while the total on-chip energy consump- tion (in mJ) is increased four times.... ..."

"... In PAGE 4: ... Both coprocessors execute at 200 MHz. Table3 highlights the speedup of our codesigned minimizers for IP routing table reduction, ACL reduction, and logic synthesis optimization with dynamic hardware/software partitioning. For IP routing table reduction, we compared ROCM-32 with our codesigned CD-ROCM-32, and for ACL reduction and dynamic hardware/software partitioning, we compared ROCM-128 with our codesigned CD-ROCM-128.... In PAGE 4: ...9. Table3 also provides the energy reduction of our codesigned minimizers over the software based ROCM-32 and ROCM-128. Orig.... ..."