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Verification of SpeedIndependent DataPath
 In IEE ProceedingsComputers and Digital Techniques
, 1996
"... This paper demonstrates that verification techniques developed for relatively large, synchronous circuits can be applied to speedindependent, selftimed circuits. We introduce local formulas which provide a natural way to specify the input/output behaviour of datapath circuits. The validity of ..."
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of a local formula is independent of the order in which the operations occur in a speedindependent circuit. We demonstrate our approach with the verification of two designs: a FIFO, and a vector multiplier chip.
Hierarchical GateLevel Verification of SpeedIndependent Circuits
 In Asynchronous Design Methodologies
, 1995
"... This paper presents a method for the verification of speedindependent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flipflops) of the circuit. Despite ..."
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Cited by 6 (3 self)
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This paper presents a method for the verification of speedindependent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flipflops) of the circuit. Despite
SIS: A System for Sequential Circuit Synthesis
, 1992
"... SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential inputoutput b ..."
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Cited by 514 (41 self)
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SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential input
Technology Mapping for SpeedIndependent Circuits: Decomposition and Resynthesis
, 1997
"... This paper presents theory and practical implementation of a method for multilevel logic synthesis of speedindependent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover conditions but is technology independent. The proposed method performs both combinational (in ..."
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Cited by 25 (10 self)
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(inserting new gates) and sequential (inserting new memory elements) decomposition of complex gates in a given standard cell library, while preserving original behaviour and speedindependence. The algorithm applies known efficient algebraic factorization techniques from combinational multilevel logic
Synthesis of Speedindependent circuits from STGunfolding segment
 Proc. 34th ACM/IEEE Design Automation Conference
, 1997
"... This paper presents a novel technique for synthesis of speedindependent circuits. It is based on partial order representation of the state graph called STGunfolding segment. The new method uses approximation technique to speed up the synthesis process. The method is illustrated on the basic implem ..."
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Cited by 4 (1 self)
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This paper presents a novel technique for synthesis of speedindependent circuits. It is based on partial order representation of the state graph called STGunfolding segment. The new method uses approximation technique to speed up the synthesis process. The method is illustrated on the basic
Estimation of Energy Consumption in SpeedIndependent Control Circuits
 IEEE Transactions on CAD
, 1995
"... : We describe a technique to estimate the energy consumed by speedindependent asynchronous (clockless) control circuits. Because speedindependent circuits are hazardfree under all possible combinations of gate delays, we prove that an accurate estimate of their energy consumption is independent o ..."
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Cited by 8 (1 self)
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: We describe a technique to estimate the energy consumed by speedindependent asynchronous (clockless) control circuits. Because speedindependent circuits are hazardfree under all possible combinations of gate delays, we prove that an accurate estimate of their energy consumption is independent
Conservative symbolic modelchecking of Petri nets for speedindependent circuit verification
, 1994
"... This paper presents a conservative symbolic modelchecking methodology for speedindependent circuits. The circuit specification is described by using Petri nets, which is the same formalism that several approaches use for synthesis. The technique is based on symbolic BDDbased reachability analysis, ..."
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Cited by 1 (0 self)
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conservative, although much more efficient. The applicability of these techniques has been proved by verifying the correctness and speedindependence of some benchmarks. 1 Introduction During these last few years, asynchronous circuits have gained interest due to their promising advantages, such us local
Efficient implementation of a BDD package
 In Proceedings of the 27th ACM/IEEE conference on Design autamation
, 1991
"... Efficient manipulation of Boolean functions is an important component of many computeraided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementat ..."
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Cited by 500 (9 self)
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Efficient manipulation of Boolean functions is an important component of many computeraided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient
Hiding Memory Elements in Induced Hierarchical Verification of SpeedIndependent Circuits
 in Proc. International Workshop on Logic Synthesis
, 1998
"... : The goal of induced hierarchical verification techniques is to automatically create hierarchy in an originally flat circuit in order to decompose the verification problem (i.e., checking hazardfreedom and conformance to a specification) into that of verifying a set of smaller subcircuits. Existi ..."
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Cited by 3 (1 self)
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. Existing induced hierarchical verification techniques for speedindependent circuits are limited because the output of any memory element (e.g., Muller Celement) must be a subcircuit output (i.e., memory elements cannot be hidden). Consequently, these techniques have exponential complexity in the number
Automatic verification of finitestate concurrent systems using temporal logic specifications
 ACM Transactions on Programming Languages and Systems
, 1986
"... We give an efficient procedure for verifying that a finitestate concurrent system meets a specification expressed in a (propositional, branchingtime) temporal logic. Our algorithm has complexity linear in both the size of the specification and the size of the global state graph for the concurrent ..."
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Cited by 1384 (62 self)
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We give an efficient procedure for verifying that a finitestate concurrent system meets a specification expressed in a (propositional, branchingtime) temporal logic. Our algorithm has complexity linear in both the size of the specification and the size of the global state graph for the concurrent
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