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Bitserial parallel processing systems
 IEEE Transactions on Computers C31
, 1982
"... AbstractAbout a decade ago, a bitserial parallel processing system STARAN ® 1 was developed. It used standard integrated circuits that were available at that time. Now, with the availability of VLSI, a much greater processing capability can be packed in a unit volume. This has Jed to the recent de ..."
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Cited by 8 (0 self)
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AbstractAbout a decade ago, a bitserial parallel processing system STARAN ® 1 was developed. It used standard integrated circuits that were available at that time. Now, with the availability of VLSI, a much greater processing capability can be packed in a unit volume. This has Jed to the recent
Deriving bitserial circuits in Ruby
, 1991
"... The action of bitserial arithmetic circuits is often explained in purely pictorial terms. In contrast, this paper describes an attempt to deal with the systematic development of bitserial arithmetic circuits within a mathematical framework which we have previously used to develop parallel circuits ..."
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Cited by 2 (1 self)
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circuits. A wellknown bitserial adder is formally shown to implement the specification of an adder, without any recourse to detailed arguments about snapshots or specific arguments about sequences of inputs. 1 DESIGN BY CALCULATION Ruby [1] is a language of relations and functions that supports a style
Implementing data cubes efficiently
 In SIGMOD
, 1996
"... Decision support applications involve complex queries on very large databases. Since response times should be small, query optimization is critical. Users typically view the data as multidimensional data cubes. Each cell of the data cube is a view consisting of an aggregation of interest, like total ..."
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Cited by 545 (1 self)
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Decision support applications involve complex queries on very large databases. Since response times should be small, query optimization is critical. Users typically view the data as multidimensional data cubes. Each cell of the data cube is a view consisting of an aggregation of interest, like total sales. The values of many of these cells are dependent on the values of other cells in the data cube..A common and powerful query optimization technique is to materialize some or all of these cells rather than compute them from raw data each time. Commercial systems differ mainly in their approach to materializing the data cube. In this paper, we investigate the issue of which cells (views) to materialize when it is too expensive to materialize all views. A lattice framework is used to express dependencies among views. We present greedy algorithms that work off this lattice and determine a good set of views to materialize. The greedy algorithm performs within a small constant factor of optimal under a variety of models. We then consider the most common case of the hypercube lattice and examine the choice of materialized views for hypercubes in detail, giving some good tradeoffs between the space used and the average time to answer a query. 1
Domain names  Implementation and Specification
 RFC883, USC/Information Sciences Institute
, 1983
"... This RFC describes the details of the domain system and protocol, and assumes that the reader is familiar with the concepts discussed in a companion RFC, "Domain Names Concepts and Facilities " [RFC1034]. The domain system is a mixture of functions and data types which are an official pr ..."
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Cited by 715 (9 self)
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This RFC describes the details of the domain system and protocol, and assumes that the reader is familiar with the concepts discussed in a companion RFC, "Domain Names Concepts and Facilities " [RFC1034]. The domain system is a mixture of functions and data types which are an official
A bitserial FFT processor
"... This work presents the results of the description in VHDL of an FFT processor, which was synthesized on Field Programmable Gate Array (FPGA). The description has generic number of points. The purpose of this work is to obtain an areaoptimized description of an FFT processor. Therefore, bitserial a ..."
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This work presents the results of the description in VHDL of an FFT processor, which was synthesized on Field Programmable Gate Array (FPGA). The description has generic number of points. The purpose of this work is to obtain an areaoptimized description of an FFT processor. Therefore, bitserial
Efficient implementation of a BDD package
 In Proceedings of the 27th ACM/IEEE conference on Design autamation
, 1991
"... Efficient manipulation of Boolean functions is an important component of many computeraided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementat ..."
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Cited by 500 (9 self)
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to decrease memory use. Memory function efficiency is improved by using rules that detect. when equivalent functions are computed. The usefulness of the package is enhanced by an automatic and lowcost scheme for rec:ycling memory. Experimental results are given to demonstrate why various implementation trade
An AreaEfficient BitSerial Integer Multiplier
"... Abstract: This paper presents the design of a new multiplier architecture for normal integer multiplication of positive and negative numbers. It has been developed to increase the performance of algorithms for cryptographic and signal processing applications on implementations of the Instruction Sys ..."
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Systolic Array (ISA) parallel computer model [6,7]. The multiplier operates least significant bit (LSB)first. It is a modular bitserial design which on the one hand can be efficiently implemented in hardware and on the other hand has the advantage that it can handle operands of arbitrary length.
Fast Parallel Algorithms for ShortRange Molecular Dynamics
 JOURNAL OF COMPUTATIONAL PHYSICS
, 1995
"... Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of interatomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dyn ..."
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Cited by 622 (6 self)
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dynamics models which can be difficult to parallelize efficiently  those with shortrange forces where the neighbors of each atom change rapidly. They can be implemented on any distributedmemory parallel machine which allows for messagepassing of data between independently executing processors
UNet: A UserLevel Network Interface for Parallel and Distributed Computing
 In Fifteenth ACM Symposium on Operating System Principles
, 1995
"... The UNet communication architecture provides processes with a virtual view of a network interface to enable userlevel access to highspeed communication devices. The architecture, implemented on standard workstations using offtheshelf ATM communication hardware, removes the kernel from the communi ..."
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Cited by 596 (17 self)
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, as well as novel abstractions like Active Messages can be implemented efficiently. A UNet prototype on an 8node ATM cluster of standard workstations offers 65 microseconds roundtrip latency and 15 Mbytes/sec bandwidth. It achieves TCP performance at maximum network bandwidth and demonstrates
Dryad: Distributed DataParallel Programs from Sequential Building Blocks
 In EuroSys
, 2007
"... Dryad is a generalpurpose distributed execution engine for coarsegrain dataparallel applications. A Dryad application combines computational “vertices ” with communication “channels ” to form a dataflow graph. Dryad runs the application by executing the vertices of this graph on a set of availa ..."
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Cited by 730 (27 self)
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Dryad is a generalpurpose distributed execution engine for coarsegrain dataparallel applications. A Dryad application combines computational “vertices ” with communication “channels ” to form a dataflow graph. Dryad runs the application by executing the vertices of this graph on a set
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