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The Efficient TAM Design for Core-Based SOCs Testing

by Jiann-chyi Rau, Po-han Wu, Chih-lung Chien, Chien-hsu Wu
"... Abstract:- This paper presents a framework and an efficient method to determine SOC test schedules. We increase the test TAM widths by the framework. Our method deals with the traditional scan chains and reconfigurable multiple scan chains. Experimental results for ITC’02 SOC TEST Benchmarks show th ..."
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Abstract:- This paper presents a framework and an efficient method to determine SOC test schedules. We increase the test TAM widths by the framework. Our method deals with the traditional scan chains and reconfigurable multiple scan chains. Experimental results for ITC’02 SOC TEST Benchmarks show

A Set of Benchmarks for Modular Testing of SOCs

by Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty - ITC'02 , 2002
"... This paper presents the ITC'02 SOC Test Benchmarks. The purpose of this new benchmark set is to stimulate research into new methods and tools for modular testing of SOCs and to enable the objective comparison of such methods and tools with respect to effectiveness and efficiency. The paper de ..."
Abstract - Cited by 69 (22 self) - Add to MetaCart
This paper presents the ITC'02 SOC Test Benchmarks. The purpose of this new benchmark set is to stimulate research into new methods and tools for modular testing of SOCs and to enable the objective comparison of such methods and tools with respect to effectiveness and efficiency. The paper

A Hybrid BIST Architecture and its Optimization for SoC Testing

by Gert Jervan , Zebo Peng, et al. - IEEE 2002 3RD INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED'02 , 2002
"... This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemented either only in software or by using some test related hardware. In our approach we combine pseudorandom test patterns w ..."
Abstract - Cited by 9 (6 self) - Add to MetaCart
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemented either only in software or by using some test related hardware. In our approach we combine pseudorandom test patterns

A gracefully degrading and energy-efficient modular router architecture for on-chip networks

by Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Mazin S. Yousif, Chita R. Das - in Proc. Int. Symp. Computer Architecture , 2006
"... Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Network-on-Chip (NoC) architectures are required to not only provide ultra-low latency, but also occupy a small footprint an ..."
Abstract - Cited by 40 (5 self) - Add to MetaCart
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Network-on-Chip (NoC) architectures are required to not only provide ultra-low latency, but also occupy a small footprint

Design Match and AutoDebug to verify and debug complex ASIC and SOC Designs

by Shaw Yang, Yi-hui Lin
"... The increase in complexity of SOCs (system on a chip) and the integration of complex IP cores such as PCI Express or multiple CPU cores demand more effective verification tools and methodologies. Complex protocols, transactions, and states defined in the architecture need to be verified against the ..."
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The increase in complexity of SOCs (system on a chip) and the integration of complex IP cores such as PCI Express or multiple CPU cores demand more effective verification tools and methodologies. Complex protocols, transactions, and states defined in the architecture need to be verified against

Cell multiprocessor communication network: Built for speed

by Michael Kistler, Michael Perrone, Fabrizio Petrini - IEEE Micro , 2006
"... Over the past decade, high-performance computing has ridden the wave of commodity computing, building clusterbased parallel computers that leverage the tremendous growth in processor performance fueled by the commercial world. As this pace slows, processor designers face complex problems in their ef ..."
Abstract - Cited by 108 (0 self) - Add to MetaCart
in their efforts to increase gate density, reduce power consumption, and design efficient memory hierarchies. Processor developers are looking for solutions that can keep up with the scientific and industrial communities’ insatiable demand for computing capability and that also have a sustainable market outside

Efficient Test Data Compression and Decompression for System-on-a-Chip using Internal Scan Chains and Golomb Coding

by Anshuman Chandra, Krishnendu Chakrabarty , 2001
"... We present a data compression method and decompression architecture for testing embedded cores in a system-ona -chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chains of the core under test, and provides significantly better results than a recent compress ..."
Abstract - Cited by 16 (5 self) - Add to MetaCart
We present a data compression method and decompression architecture for testing embedded cores in a system-ona -chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chains of the core under test, and provides significantly better results than a recent

SWITCH ARCHITECTURE

by unknown authors
"... OCP presents an efficient solution to address SoC contemporary design issues and shorter time-to-market requirements using an industry standard socket. The on chip permutation follows the industrial OCP protocol. The design which complies with the bus interface protocol to carry out the various adva ..."
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OCP presents an efficient solution to address SoC contemporary design issues and shorter time-to-market requirements using an industry standard socket. The on chip permutation follows the industrial OCP protocol. The design which complies with the bus interface protocol to carry out the various

Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip

by Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen - IEEE TRANSACTIONS ON COMPUTER , 2003
"... We describe an integrated framework for system-on-chip (SOC) test automation. Our framework is based on a new test access mechanism (TAM) architecture consisting of flexible-width test buses that can fork and merge between cores. Test wrapper and TAM cooptimization for this architecture is perform ..."
Abstract - Cited by 26 (7 self) - Add to MetaCart
to designate a group of tests as preemptable. Test preemption helps avoid hardware and power consumption conflicts, thereby leading to a more efficient test schedule. Finally, we study the relationship between TAM width and tester data volume to identify an effective TAM width for the SOC.

Integrated Test Scheduling, Wrapper Design, and TAM Assignment for Hierarchical SOC

by unknown authors
"... Abstract — System-On-Chip (SOCs) test minimization has received a lot of attention in the past few years. However, most recent work assumed flat hierarchy. This assumption is unrealistic especially in the case of non-mergeable legacy cores that have been placed and routed. This paper presents an eff ..."
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an efficient approach for test scheduling hierarchical core-based systems based on simulated annealing. The method minimizes the overall test application time while performing wrapper design and TAM assignment. We present experimental results for various SOC examples that demonstrate the effectiveness of our
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