Abstract:- This paper presents a framework and an efficient method to determine SOC test schedules. We increase the test TAM widths by the framework. Our method deals with the traditional scan chains and reconfigurable multiple scan chains. Experimental results for ITC’02 SOC TEST Benchmarks show

This paper presents the ITC'02 SOC Test Benchmarks. The purpose of this new benchmark set is to stimulate research into new methods and tools for modular testing of SOCs and to enable the objective comparison of such methods and tools with respect to effectiveness and efficiency. The paper

This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemented either only in software or by using some test related hardware. In our approach we combine pseudorandom test patterns

Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Network-on-Chip (NoC) architectures are required to not only provide ultra-low latency, but also occupy a small footprint

The increase in complexity of SOCs (system on a chip) and the integration of complex IP cores such as PCI Express or multiple CPU cores demand more effective verification tools and methodologies. Complex protocols, transactions, and states defined in the architecture need to be verified against

in their efforts to increase gate density, reduce power consumption, and design efficient memory hierarchies. Processor developers are looking for solutions that can keep up with the scientific and industrial communities’ insatiable demand for computing capability and that also have a sustainable market outside

We present a data compression method and decompression architecture for testing embedded cores in a system-ona -chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chains of the core under test, and provides significantly better results than a recent

OCP presents an efficient solution to address SoC contemporary design issues and shorter time-to-market requirements using an industry standard socket. The on chip permutation follows the industrial OCP protocol. The design which complies with the bus interface protocol to carry out the various

to designate a group of tests as preemptable. Test preemption helps avoid hardware and power consumption conflicts, thereby leading to a more efficient test schedule. Finally, we study the relationship between TAM width and tester data volume to identify an effective TAM width for the SOC.

an efficient approach for test scheduling hierarchical core-based systems based on simulated annealing. The method minimizes the overall test application time while performing wrapper design and TAM assignment. We present experimental results for various SOC examples that demonstrate the effectiveness of our