Results 1 - 10 of 1,712

Multiscalar Processors

by Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar - In Proceedings of the 22nd Annual International Symposium on Computer Architecture , 1995
"... Multiscalar processors use a new, aggressive implementation paradigm for extracting large quantities of instruction level parallelism from ordinary high level language programs. A single program is divided into a collection of tasks by a combination of software and hardware. The tasks are distribute ..."
Abstract - Cited by 589 (30 self) - Add to MetaCart
are distributed to a number of parallel processing units which reside within a processor complex. Each of these units fetches and executes instructions belonging to its assigned task. The appearance of a single logical register file is maintained with a copy in each parallel processing unit. Register results

The Gamma database machine project

by David J. Dewitt, Shahram Ghandeharizadeh, Donovan Schneider, Allan Bricker, Hui-i Hsiao, Rick Rasmussen - IEEE Transactions on Knowledge and Data Engineering , 1990
"... This paper describes the design of the Gamma database machine and the techniques employed in its implementation. Gamma is a relational database machine currently operating on an Intel iPSC/2 hypercube with 32 processors and 32 disk drives. Gamma employs three key technical ideas which enable the arc ..."
Abstract - Cited by 272 (29 self) - Add to MetaCart
are linear; thus, doubling the number of processors

The microarchitecture of the pentium 4 processor

by Dave Sager, Desktop Platforms Group, Intel Corp - Intel Technology Journal , 2001
"... ALU, deep pipelining This paper describes the Intel ® NetBurst™ microarchitecture of Intel’s new flagship Pentium ® 4 processor. This microarchitecture is the basis of a new family of processors from Intel starting with the Pentium 4 processor. The Pentium 4 processor provides a substantial performa ..."
Abstract - Cited by 187 (0 self) - Add to MetaCart
on some of the key features that allow the Pentium 4 processor to have outstanding floating-point and multi-media performance. We provide some key performance numbers for this processor, comparing it to the Pentium ® III processor.

Megabase chromatin domains involved in DNA double-strand breaks in vivo

by Emmy P. Rogakou, Chye Boon, Christophe Redon, William M. Bonner - J. Cell , 1999
"... Abstract. The loss of chromosomal integrity from DNA double-strand breaks introduced into mammalian cells by ionizing radiation results in the specific phosphorylation of histone H2AX on serine residue 139, yielding a specific modified form named �-H2AX. An antibody prepared to the unique region of ..."
Abstract - Cited by 203 (2 self) - Add to MetaCart
min after exposure of cells to ionizing radiation. The numbers of these foci are comparable to the numbers of induced DNA double-strand breaks. When DNA double-strand breaks are introduced into specific partial nuclear volumes of cells by means of a pulsed microbeam laser, �-H2AX foci form

Checkpoint processing and recovery: Towards scalable large instruction window processors

by Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan - In Proceedings of the 36th International Symposium on Microarchitecture , 2003
"... Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically required to buffer and process such instruction window sizes significantly degrade the cycle time. This paper proposes a nov ..."
Abstract - Cited by 175 (8 self) - Add to MetaCart
from branch mispredicts, 3) buffering a large number of stores and forwarding data from stores to any dependent load, and 4) reclaiming physical registers. While scheduling window size is important, we show the performance of large instruction windows to be more sensitive to the other three design

Multiple-banked register file architectures

by José-Lorenzo Cruz , Antonio González , Mateo Valero , Nigel P Topham - In International Symposium on Computer Architecture(ISCA-27 , 2000
"... Abstract The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor generations, as they are expected to increase the issue width (which implies more register ports) and the size of the ..."
Abstract - Cited by 146 (12 self) - Add to MetaCart
Abstract The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor generations, as they are expected to increase the issue width (which implies more register ports) and the size

Reducing the Complexity of the Register File in Dynamic Superscalar Processors

by Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi , 2001
"... Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a direct impact on the size of this window as most in-flight instructions require a new physical register a ..."
Abstract - Cited by 96 (1 self) - Add to MetaCart
Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a direct impact on the size of this window as most in-flight instructions require a new physical register

Register Organization for Media Processing

by Scott Rixner , William J. Dally, Brucek Khailany, Peter Mattson, Ujval J. Kapasi, John D. Owens - HPCA6 , 2000
"... Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, and image understanding, require arithmetic rates of up to 10 11 operations per second. As the number of arithmetic uni ..."
Abstract - Cited by 126 (11 self) - Add to MetaCart
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, and image understanding, require arithmetic rates of up to 10 11 operations per second. As the number of arithmetic

Optimization Principles and Application Performance Evaluation of a Multithreaded GPU Using CUDA

by Shane Ryoo, Christopher I. Rodrigues, Sara S. Baghsorkhi, Sam S. Stone, et al. - PPOPP'08 , 2008
"... GPUs have recently attracted the attention of many application developers as commodity data-parallel coprocessors. The newest generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power of tradition ..."
Abstract - Cited by 215 (11 self) - Add to MetaCart
of simultaneously active threads. The resources to manage include the number of registers and the amount of on-chip memory used per thread, number of threads per multiprocessor, and global memory bandwidth. We also obtain increased performance by reordering accesses to off-chip memory to combine requests

Processor

by J. Laxmi, R. Ramprakash
"... Abstract: In this paper, we deal with the designing of a 32-bit floating point arithmetic processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating point operations are incorporated into the design as functions. The logic for these is differe ..."
Abstract - Add to MetaCart
Abstract: In this paper, we deal with the designing of a 32-bit floating point arithmetic processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating point operations are incorporated into the design as functions. The logic
Results 1 - 10 of 1,712