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Table 1. Important Parameters of the LDPC Decoder Design Space

in Disclosing the LDPC Code Decoder Design Space
by unknown authors

Table 2. LDPC decoder hardware resource compari- son.

in Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding
by Marjan Karkooti And, Marjan Karkooti, Joseph R. Cavallaro 2004
"... In PAGE 3: ... With this approach, the hardware design can be fixed to relate to a special case of the parity check matrix. Table2 shows a comparison between the resources for a parallel, semi-parallel or serial implementation of the de- coder. In this table , CF CR is the degree of Bit nodes, CF D6 is the degree of the Check nodes, CQ is the number of the bits per message and CB is the folding factor for the semi-parallel design.... ..."
Cited by 5

TABLE III DESIGN STATISTICS FOR THE FLEXIBLE LDPC DECODER ON VIRTEX4-XC4VFX60 FPGA.

in Tradeoff Analysis and Architecture Design of High Throughput Irregular LDPC Decoders
by Predrag Radosavljevic, Student Member, Marjan Karkooti, Student Member, Re De Baynast, Joseph R. Cavallaro, Senior Member

Table 3.1 : LDPC decoder hardware resource comparison. Design Fully Semi Fully

in Semi-Parallel Architectures
by Marjan Karkooti 2004

TABLE 1 Summary of LDPC decoders.

in 3.2-Gb/s 1024-b Rate-1/2 LDPC Decoder Chip Using a Flooding-Type Update-Schedule Algorithm
by Naoya Onizawa, Tomokazu Ikeda, Takahiro Hanyu

Table 1: Typical scanning formats used for digital video communications.

in Source Compression - Video
by Eric Dubois
"... In PAGE 3: ... Although some standards allow considerable exibility in the choice of picture format, a number of speci c formats are in common use or have been proposed. Table1 shows the parameters of some of these formats. The nal coded bit rate is very directly related to the source sampling rate, although not linearly.... In PAGE 19: ... The standard de nes only the functionality of the decoder; the encoder is not explicitly de ned, but it must produce a bit stream compatible with the standard decoder. The input signals are in QCIF or CIF format ( Table1 ). The coding algorithm uses motion-compensated temporal DPCM, with DCT coding of the residual.... ..."

Table 1. Computation Requirements of the LDPC Decoder.

in Efficient DSP Implementation of an LDPC Decoder
by Gottfried Lechner, Jossy Sayir, Markus Rupp 2004
"... In PAGE 3: ... This makes the comparison between LDPC decoder and Turbo decoder di cult. The computation requirements of our implementa- tion are summarized in Table1 . The values given in the table do not account for the parallel computation of two nodes described in Subsection 3.... ..."
Cited by 1

TABLE II Resources consumed by LDPC Decoder Components

in Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware
by Benjamin Levine , R. Reed Taylor, Herman Schmit

TABLE II SUMMARY OF LDPC DECODER CHARACTERISTICS.

in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II 1 Block-Interlaced LDPC Decoders with Reduced Interconnect Complexity
by Ahmad Darabiha, Student Member, Anthony Chan Carusone, Frank R. Kschischang

TABLE I SUMMARY OF MEASURED RESULTS FOR THE (660, 480) LDPC DECODER.

in A 3.3-Gbps Bit-Serial Block-Interlaced Min-Sum LDPC Decoder in 0.13-µm CMOS
by Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang
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