### Table 1 Design objectives of the BLV861 amplifier

"... In PAGE 3: ...3 Philips Semiconductors A Broadband 100 W Push Pull Amplifier for Band IV amp; V TV Transmitters based on the BLV861 Application Note AN98033 1 INTRODUCTION Intended for applications in TV transmitter output stages a broadband high power amplifier has been described with a single BLV861 transistor. The design objectives are given in Table1 . In the following sections a background information of the BLV861 will be given, followed by a description and tuning of the application circuit.... ..."

### Table 3: A 15-bit error-correcting output code for a ten-class problem.

1995

"... In PAGE 4: ... Table3 shows a 15-bit error-correcting code for the digit-recognition task. Each class is represented byacodeword drawn from an error-correcting code.... In PAGE 4: ... If we make only b d,1 2 c errors, the nearest codeword will still be the correct codeword. #28The code of Table3 has minimum Hamming distance seven and hence it can correct errors in any three bit positions.#29 The Hamming distance between anytwo codewords in the one- per-class code is two, so the one-per-class encoding of the k output classes cannot correct any errors.... In PAGE 7: ... 2.3 Error-Correcting Code Design We de#0Cne an error-correcting code to be a matrix of binary values such as the matrix shown in Table3 . The length of a code is the number of columns in the code.... ..."

Cited by 353

### Table 4. Initial output action sets amp; operational semantics (action transitions)

"... In PAGE 8: ... In order to present our communication mechanism, we need to introduce initial output action sets, II(P), for P 2 P. These are de ned as the least sets satisfying the equations in Table4 (upper part). Intuitively, II(P) collects all events which are initially o ered by P.... In PAGE 8: ...The semantics for action transitions, depicted in Table4 (lower part), is set up such that P E ?! N P0 means: P can evolve to P0, if the environment o ers communications on all ports in E, but none on any port in N. More precisely, process hE; Ni:P may engage in input action hE; Ni and then behave like P.... ..."

### Table 4.16: Design 1 outputs for variations in the parasitic interconnect capacitance of the differential ampli- fier illustrated in Figure 4.4.

2004

### Table 4.17: Design 2 outputs for variations in the parasitic interconnect capacitance of the differential ampli- fier illustrated in Figure 4.4.

2004

### Table 2: De nition of output classes of XOR problem.

in A Constructive Algorithm for the Training of a Multilayer Perceptron Based on the Genetic Algorithm

1993

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### Table 2: The capacitance ranges for oscillation in Figure 4

1998

"... In PAGE 6: ... We de ne oscillation as the case where the swing at out apos;s voltage exceeds the swing at float apos;s voltage. The last two columns in Table2 show that CVDD needs to be smaller than CGND for an oscillation, but not too small. The last row shows that CVDD to CVDD + CGND ratio needs to be 0.... In PAGE 7: ... Therefore, in general it is reasonable to expect that CVDD will be smaller than CGND on average, but close to it, which is exactly the oscillation requirement we discussed in the preceding paragraph as illustrated by Table 2. The last row in Table2 requires a very narrow range for CVDD, but 400fF corresponds to a very long wire in the HP 0.6 technology, which would be a more than 3mm long metal-1 wire... In PAGE 8: ...b1 = 1 a1 = 0 b1 = 1 a1 = 0 a2 S2 float q b2 Figure 6: Miller capacitances to node float in Figure 4 over substrate. In general, oscillation due to Miller feedback capacitances is more likely when (CVDD +CGND) is small as also shown by Table2 , because the Miller feedback capacitance sizes are xed by the transistor sizes. 3 Sequential Behavior due to Interconnect Opens In this section we show how an interconnect open can cause sequential behavior.... In PAGE 13: ... In Table 4 we computed the range of CVDD for di erent (CVDD +CGND) values such that this XOR gate displays sequential behavior, that is, the vector line intersects the non- oating Qs at three points, one being metastable and the other two being logic-0 and logic-1. Interestingly, the values in Table 4 are very similar to the ones in Table2 , showing a duality between oscillation... In PAGE 16: ... Finally, oscillation is most probable when the oating input voltage is around the logic threshold, as we explained in the preceding section. These three facts imply that CGND needs to be larger than CVDD for oscillation, as illustrated by Table2 , which also shows that smaller the CVDD + CGND is, more likely oscillation is. For this reason, we decided to make CVDD in Figure 13 as small as possible.... ..."

Cited by 2

### Table 1 : CMOS Operational Amplifier

"... In PAGE 3: ...The nominal values of all transistor widths, corre- sponding to an initial feasible solution, are shown in the #0Cgure. We performed the LHE and the CP design centering procedures in the transformed domain, to obtain the results shown in Table1 . The LHE design center was found to be #5B101:0#16m; 94:1#16m; 103:4#16m#5D.... ..."

### Table 1: Technical parameters The values for the resistances are chosen for all MOSFETs as Rs = Rd = 4 ; Rsd = 1015 : The capacitance between gate and source as well as the capacitance between gate and drain are modelled as linear capacitors, i.e., qgs(u) = qgd(u) = C1 u with C1 = 0:6 10?13F: The capacitance between bulk and drain as well as the capacitance between bulk and source are modelled by nonlinear capacitances qbd(u) = qbs(u) = 8 lt; : C0 B 1 ? q1 ? u B for u 0

1997

Cited by 6

### Table 9 Test data for large scale capacitive prototype

2003

"... In PAGE 12: ... 6 is viable, rather than to build a device optimized for output power. Table9 shows the essential testing data for this device. Both in-plane overlap and gap closing converters have been designed and are in fabrication using the DRIE process previously mentioned.... ..."

Cited by 29