### Table 3: Average di erence in rankings of topologies according to di erent delay models. The sample consists of 20 random nets of each cardinality. Note that the total number of topologies for each net is 16 for jNj = 4 and 125 for jNj = 5. di erence for the ve topologies which have lowest delay according to the rst estimate. Our results show that Elmore delay has high delity, particularly when we compare the SPICE ranking of the optimal topology for Elmore delay with the optimal topology for linear delay: for nets of size 5 using technology IC3, optimal topologies under Elmore delay were always optimal according to SPICE in our sample! In comparison, the best topology under linear delay was distance 29 away on average from its correct SPICE ranking. For 5-pin nets under the IC1 and IC2 technologies, best topology under Elmore delay also has a very high SPICE ranking: on average the distance from its SPICE ranking is 2.6 for IC1 (versus 5.3 under linear delay) and 1.9 for IC2 (versus 11.3 under linear delay). 3 We have 3For IC2, the distance of 1:87 positions implies a di erence of approximately 3.8% in actual SPICE-computed delay. For IC1, the di erence of 2:57 positions leads to an average 8.57% penalty in SPICE-computed delay. In the Appendix, we give three tables showing the drop-o in SPICE delay quality for each rank, when compared with optimal delay. 7

"... In PAGE 7: ...) We have run simulations to estimate this measure of delity for Elmore delay for nets of size 4 and 5 using each of the three IC technologies. Table3 assesses the delity to SPICE of the rankings of tree topologies according to the linear and Elmore delay models. We report the average di erence in ranking over all topologies; the average di erence for the topology which has lowest delay according to the rst estimate; and the average... ..."

### Table 1: Di erent CSMA schemes with variations on the amount of delay period, listening period, and ways of backo . All exponential backo s are binary exponential.

2001

"... In PAGE 6: ...0kbps channel capacity can deliver at most 20.8 packet/s. We use a 16-bit CRC error detection mechanism to check for corrupted packets. The speci c the values of all the neces- sary parameters for the CSMA schemes in Table1 are given in Table 2. 5.... In PAGE 6: ... 5.2 Delivered Bandwidth under Simulation The average aggregate bandwidth received at the base sta- tion for each scheme in Table1 is shown in Figure 4. The... In PAGE 8: ... Nodes are set to send at di erent rates to cre- ate an uneven amount of tra c. Table 3 lists the send rate of each node and the resulting bandwidth allocation among di erent nodes for each scheme in Table1 . All data is nor- malized to the bandwidth of node 10 in order to observe the relative proportion of bandwidth allocation.... ..."

Cited by 272

### Table 1: Communication delays for some topologies [86].

"... In PAGE 46: ... 20. For comparison, the communication delay for the basic tasks are summarized in Table1 for all of these topolo- gies. A bus is the simplest static network where processing units are connected in a time-multiplexed manner.... In PAGE 47: ... The connectivity of the tree is as poor as in array, since breaking any one connection results two separate networks, but the flexibility is better. In Table1 , communication delays are given for optimized algorithms for a system with processing units, for which reason single node scatter and multinode broadcast can be accomplished in time . In general, upper bound for both operations is .... In PAGE 48: ... The implementation, however, becomes very complicated as the number of nodes is increased. For comparison, Table1 summarizes communication delays for above topol- ogies [86]. The bus offers best communication delay in single node broad- cast, while the tree and hypercube perform better than mesh and array.... ..."

### Table 4.3: Comparison of decomposition heuristics under a general delay model.

"... In PAGE 59: ...8.1 Results for Uniform Decomposition Table4 contains the total power consumed in the bottom-up decomposition, the optimal uniform decomposition, and the worst case uniform decomposition. A number in parenthesis indicates the percentage di#0Berence in power from the optimal decomposition.... ..."

### Table 2: Virtual topology for nodal degree = 4 and best scaleup (106).

1996

"... In PAGE 9: ... The scaleup provides an estimate of the throughput in the network. We note from these gures, as well as from Table2 , that the propagation delay is the dominant com- ponent of the packet delay. Also, at light loads, the average propagation delay faced by packets in NSFNET is a little over 9 ms (for the given tra c matrix), and this serves as a lower bound on the average packet delay.... ..."

Cited by 55

### Table 1: Delay Optimization

"... In PAGE 3: ... We use a high mapping ef- fort and a virtual clock with a small clock period to enforce Synopsys to try its best in terms of delay opti- mization. The results of our delay optimization efforts can be found in Table1 . Column 1 shows the circuit name and column 2 has the number of transformations the circuit undergoes to reach the final optimized ver- sion.... In PAGE 4: ...Table1 contains the overall run-time. Table 2: Results on Power Minimization ckt # of original final % area delay time name modif.... ..."

### Table 1: Delay Optimization

"... In PAGE 3: ... We use a high mapping ef- fort and a virtual clock with a small clock period to enforce Synopsys to try its best in terms of delay opti- mization. The results of our delay optimization efforts can be found in Table1 . Column 1 shows the circuit name and column 2 has the number of transformations the circuit undergoes to reach the final optimized ver- sion.... In PAGE 4: ...Table1 contains the overall run-time. Table 2: Results on Power Minimization ckt # of original final % area delay time name modif.... ..."

### TABLE II ROADMAP SHOWING MINIMUM METRICS OR MOST SUITABLE TOPOLOGIES FOR 64-NODE NETWORKS AT 90nm AND 50nm TECHNOLOGIES. THE 4-TUPLE UNDER EACH TOPOLOGY DENOTES THE ROUTING TYPE WHERE A = ADAPTIVE AND D = DETERMINISTIC, THE FLOW CONTROL TYPE WHERE W = WORMHOLE AND V = VIRTUAL CUT-THOUGH , THE BUFFER SIZE PER VIRTUAL CHANNEL (VC) IN TERMS OF 64-BIT FLITS AND THE VC COUNT PER PHYSICAL CHANNEL. EC DENOTES EXPRESS CUBE TOPOLOGIES, WHERE e DENOTES THE LINK INTERVAL.

### Table 4.6: Total power of greedy and H#28100; 1#29 under a general delay model.

"... In PAGE 59: ...8.1 Results for Uniform Decomposition Table4 contains the total power consumed in the bottom-up decomposition, the optimal uniform decomposition, and the worst case uniform decomposition. A number in parenthesis indicates the percentage di#0Berence in power from the optimal decomposition.... ..."

### Table 4.9: Combinational power of greedy and H#28100; 1#29 under a general delay model.

"... In PAGE 59: ...8.1 Results for Uniform Decomposition Table4 contains the total power consumed in the bottom-up decomposition, the optimal uniform decomposition, and the worst case uniform decomposition. A number in parenthesis indicates the percentage di#0Berence in power from the optimal decomposition.... ..."