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258
SIS: A System for Sequential Circuit Synthesis
, 1992
"... SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential inputoutput b ..."
Abstract

Cited by 527 (44 self)
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SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential input
Symbolic model checking for sequential circuit verification
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 1994
"... The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDD’s) [7] and partitioned trunsirion relations [lo], 1111. Because this representation captures some of the regularity in the state space of circuit ..."
Abstract

Cited by 271 (12 self)
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of circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5 x 10^120 states. Our model checking algorithm handles full CTL with fairness constraints. Consequently, we
Derivatives of regular expressions
 JOURNAL OF THE ACM
, 1964
"... Abstract. Kleene's regular expressions, which can be used for describing sequential circuits, were defined using three operators (union, concatenation and iterate) on sets of sequences. Word descriptions of problems can be more easily put in the regular expression language if the language is en ..."
Abstract

Cited by 305 (10 self)
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Abstract. Kleene's regular expressions, which can be used for describing sequential circuits, were defined using three operators (union, concatenation and iterate) on sets of sequences. Word descriptions of problems can be more easily put in the regular expression language if the language
Estimation of Average Switching Activity in Combinational and Sequential Circuits
 In Proceedings of the 29 th Design Automation Conference
, 1992
"... power dissipated in VLSI combinational and sequential circuits, under random input sequences. Switching activity is strongly affected by gate delays and for this reason we use a general delay model in estimating switching activity. Our method takes into account correlation caused at internal gates i ..."
Abstract

Cited by 108 (9 self)
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in the circuit due to reconvergence of input signals. In sequential circuits, the input sequence applied to the combinational portion of the circuit is highly correlated because some of the inputs to the combinational logic are flipflop outputs representing the state of the circuit. We present methods
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits
 ACM/IEEE 31st Design Automation Conference
, 1994
"... We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a nonlinear system of equations of size N , where the variables correspond to state line probabilities. We show that the approximation method is within 3% o ..."
Abstract

Cited by 39 (1 self)
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We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a nonlinear system of equations of size N , where the variables correspond to state line probabilities. We show that the approximation method is within 3
Design Replacements for Sequential Circuits
, 1996
"... In this dissertation we study the problem of design replacements for synchronous sequential circuits. There have been previous efforts to characterize the criterion for replacement for such circuits. However, all previous attempts either make implicit or explicit assumptions about the design or the ..."
Abstract

Cited by 11 (4 self)
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In this dissertation we study the problem of design replacements for synchronous sequential circuits. There have been previous efforts to characterize the criterion for replacement for such circuits. However, all previous attempts either make implicit or explicit assumptions about the design
Debugging sequential circuits using boolean satisfiability
 In Proceedings of the 2004 IEEE/ACM International conference on Computeraided design
, 2004
"... Logic debugging of today's complex sequential circuits is an important problem. In this paper, a logic debugging methodology for multiple errors in sequential circuits with no state equivalence is developed. The proposed approach reduces the problem of debugging to an instance of Boolean Satis ..."
Abstract

Cited by 42 (14 self)
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Logic debugging of today's complex sequential circuits is an important problem. In this paper, a logic debugging methodology for multiple errors in sequential circuits with no state equivalence is developed. The proposed approach reduces the problem of debugging to an instance of Boolean
FSM based Checker for Sequential Circuits
, 2001
"... This paper presents a method for logic synthesis of Totally Selfchecking Checkers for sequential circuits in a form of a Finite State Machine. This approach allows sufficient reduction of both the number of redundant bits of the sequential circuit, and the number of inputs of the checker. ..."
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This paper presents a method for logic synthesis of Totally Selfchecking Checkers for sequential circuits in a form of a Finite State Machine. This approach allows sufficient reduction of both the number of redundant bits of the sequential circuit, and the number of inputs of the checker.
Techniques for the Power Estimation of Sequential Logic Circuits Under UserSpecified Input Sequences and Programs
 IEEE Transactions on VLSI Systems
, 1994
"... We describe an approach to estimate the average power dissipation in sequential logic circuits under userspecified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or proc ..."
Abstract

Cited by 38 (9 self)
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We describe an approach to estimate the average power dissipation in sequential logic circuits under userspecified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller
Analysis Of Combinational Cycles In Sequential Circuits
, 1996
"... This paper addresses the analysis of combinational cycles in synchronous, sequential circuits. A circuit that has a combinational cycle does not necessarily have unstable output behavior: the cycle may be "false" for all reachable states and possible input sequences, or the unstable behavi ..."
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Cited by 8 (1 self)
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This paper addresses the analysis of combinational cycles in synchronous, sequential circuits. A circuit that has a combinational cycle does not necessarily have unstable output behavior: the cycle may be "false" for all reachable states and possible input sequences, or the unstable
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