### Table 1. Complexity of point multiplication in GF(2m)(a; b 6 =0)

"... In PAGE 4: ... gt;From Table1 it is clear that an efficient method for squaring will have a con- siderable impact on the overall performance. Through the use of reconfigurable hardware it is possible to compute a square in one clock cycle for any field or- der even though a standard basis representation is being used.... In PAGE 12: ...7 times faster than the traditional double-and-add algorithm. One can deduce from Table1 that this is a direct result of the number of mul- tiplications required by each algorithm ( 10:5=6), as the processing time for additions, squares, and inversions is almost negligible. Table 4 also shows that the speedup increases as the digit size increases.... ..."

### TABLE 1. KEY PARAMETERS FOR DIFFERENT ARCHITECTURES OF SERIAL GF(2M) MULTIPLIERS USING DIFFERENT BASES

### Table 6.4: Area estimates for scalar GF(2m) multiply-accumulate units.

2005

### TABLE 15.3 Propagation of Errors Injected into PACNT.

### Table 3. Number of clock cycles required to compute kP over GF(2m)

2000

"... In PAGE 12: ...Table3 approximates the number of cycles required for the computation of point multiplication for arbitrary GF(2m) fields. The approximations are based exclusively on the number of multiplications and the number of clock cycles required to compute them with an LSD multiplier with digit size D.... ..."

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### Table 3. Number of clock cycles required to compute kP over GF(2m)

"... In PAGE 12: ...Table3 approximates the number of cycles required for the computation of point multiplication for arbitrary GF(2m) elds. The approximations are based exclusively on the number of multiplications and the number of clock cycles required to compute them with an LSD multiplier with digit size D.... ..."

### Table 1: Comparison of Parity Codes In high-speed memories, single-bit error-correcting and double-bit error-detecting (SEC-DED) codes are most commonly used. The data before writing to the memory are passed to a parity generator. The generated parity bit (or bits) is (are) then stored in the memory together with the data. On read operation the data bits are passed into the parity checker that regenerates the parity bit (or bits) and compares it with the parity bit(s) stored in the memory when the original data were written to the memory. The single-bit parity code has a minimum Hamming distance of two. The following description brings more details on Hamming codes. In Hamming single-error correction code, c parity bits are added to a k-bit data word, forming a code word of k+c bits. The following expression can be used to determine number of necessary check (parity) bits to protect k bits of information:

"... In PAGE 10: ... 10 computers to check errors in busses, memory, and registers. Table1 compares parity codes for memories. Five strategies for calculating parity are considered: (1) bit-per-word parity, (2) bit-per- byte, (3) bit-per-multiple-chips, (4) bit-per-chip, and (5) interlaced parity.... ..."

### Table 1: Comparison of Parity Codes In high-speed memories, single-bit error-correcting and double-bit error-detecting (SEC-DED) codes are most commonly used. The data before writing to the memory are passed to a parity generator. The generated parity bit (or bits) is (are) then stored in the memory together with the data. On read operation the data bits are passed into the parity checker that regenerates the parity bit (or bits) and compares it with the parity bit(s) stored in the memory when the original data were written to the memory. The single-bit parity code has a minimum Hamming distance of two. The following description brings more details on Hamming codes. In Hamming single-error correction code, c parity bits are added to a k-bit data word, forming a code word of k+c bits. The following expression can be used to determine number of necessary check (parity) bits to protect k bits of information:

"... In PAGE 10: ... 10 computers to check errors in busses, memory, and registers. Table1 compares parity codes for memories. Five strategies for calculating parity are considered: (1) bit-per-word parity, (2) bit-per- byte, (3) bit-per-multiple-chips, (4) bit-per-chip, and (5) interlaced parity.... ..."

### Table 2: Overview of flexible multiplication units supporting several fields in GF(2m).

"... In PAGE 5: ... It is premised that smaller polynomials are padded with zeros to meet the full multiplication factor length. Table2 shows an overview of multipliers for different fields applying the reduction methods as they were described in the previous section. One can see that the MHWR approach is very efficient.... ..."

### Table 4: Timings (in seconds) for inversion with MT-X in GF(2m).

"... In PAGE 17: ... the inversion. A series of experimental results are presented in Table4 where MT-X denotes the X-input Montgomery trick. Each data set is organized in two rows.... In PAGE 17: ...Table 4: Timings (in seconds) for inversion with MT-X in GF(2m). As shown in Table4 , the timing improvement is negligible while exceeding MT-16. Therefore, the 16-input Montgomery trick was used in the point addition program.... ..."

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