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82
1Citadel: Efficiently Protecting Stacked Memory From Large Granularity Failures
"... Abstract—Stacked memory modules are likely to be tightly integrated with the processor. It is vital that these modules operate reliably, where failure can require replacement of the entire socket. To make matters worse, stacked memory designs are susceptible to new failure modes (for example, due to ..."
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protection from large-granularity failures. Citadel consists of three components; TSV-Swap, which can tolerate both faulty data-TSVs and faulty address-TSVs; Three Dimensional Parity (3DP), which can tolerate column failures, row failures, and bank failures; and Dynamic Dual-Granularity Sparing (DDS), which
Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures
"... Abstract—Stacked memory modules are likely to be tightly integrated with the processor. It is vital that these memory modules operate reliably, as memory failure can require the replacement of the entire socket. To make matters worse, stacked memory designs are susceptible to newer failure modes (fo ..."
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and efficiently protects the stacked memory from large-granularity failures. Citadel consists of three components; TSV-Swap, which can tolerate both faulty data-TSVs and faulty address-TSVs; Tri Dimensional Parity (3DP), which can tolerate column failures, row failures, and bank failures; and Dynamic Dual-Granularity
Resilient die-stacked dram caches
"... Die-stacked DRAM can provide large amounts of in-package, high-bandwidth cache storage. For server and high-performance com-puting markets, however, such DRAM caches must also provide sufficient support for reliability and fault tolerance. While con-ventional off-chip memory provides ECC support by ..."
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Die-stacked DRAM can provide large amounts of in-package, high-bandwidth cache storage. For server and high-performance com-puting markets, however, such DRAM caches must also provide sufficient support for reliability and fault tolerance. While con-ventional off-chip memory provides ECC support
Frugal ECC: Efficient and Versatile Memory Error Protection through Fine-Grained Compression
"... Because main memory is vulnerable to errors and failures, large-scale systems and critical servers utilize error checking and correcting (ECC)mechanisms tomeet their reliability requirements. We propose a novelmechanism, Frugal ECC (FECC), that combines ECCwith fine-grained compression to provide ve ..."
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Because main memory is vulnerable to errors and failures, large-scale systems and critical servers utilize error checking and correcting (ECC)mechanisms tomeet their reliability requirements. We propose a novelmechanism, Frugal ECC (FECC), that combines ECCwith fine-grained compression to provide
Unison cache: A scalable and effective die-stacked dram cache
- in Microarchitecture (MICRO), 2014 47th Annual IEEE/ACM International Symposium on, Dec 2014
"... Abstract—Recent research advocates large die-stacked DRAM caches in manycore servers to break the memory latency and bandwidth wall. To realize their full potential, die-stacked DRAM caches necessitate low lookup latencies, high hit rates and the efficient use of off-chip bandwidth. Today’s stacked ..."
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Cited by 1 (0 self)
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Abstract—Recent research advocates large die-stacked DRAM caches in manycore servers to break the memory latency and bandwidth wall. To realize their full potential, die-stacked DRAM caches necessitate low lookup latencies, high hit rates and the efficient use of off-chip bandwidth. Today’s stacked
Die-Stacked DRAM Caches for Servers Hit Ratio, Latency, or Bandwidth? Have It All with Footprint Cache
"... Recent research advocates using large die-stacked DRAM caches to break the memory bandwidth wall. Existing DRAM cache designs fall into one of two categories — block-based and pagebased. The former organize data in conventional blocks (e.g., 64B), ensuring low off-chip bandwidth utilization, but co- ..."
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Cited by 11 (1 self)
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, and leverage high spatial locality at the cost of moving large amounts of data on and off the chip. This paper introduces Footprint Cache, an efficient die-stacked DRAM cache design for server processors. Footprint Cache allocates data at the granularity of pages, but identifies and fetches only those blocks
An efficient XOR-Scheduling algorithm for erasure codes encoding
- in DSN-2009: The International Conference on Dependable Systems and Networks
, 2009
"... In large storage systems, it is crucial to protect data from loss due to failures. Erasure codes lay the foundation of this protection, enabling systems to reconstruct lost data when components fail. Erasure codes can however impose significant performance overhead in two core operations: Encoding, ..."
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Cited by 6 (3 self)
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In large storage systems, it is crucial to protect data from loss due to failures. Erasure codes lay the foundation of this protection, enabling systems to reconstruct lost data when components fail. Erasure codes can however impose significant performance overhead in two core operations: Encoding
1 Efficiently Securing Systems from Code Reuse Attacks
"... Abstract—Code reuse attacks (CRAs) are recent security exploits that allow attackers to execute arbitrary code on a compromised machine. CRAs, exemplified by return-oriented and jump-oriented programming approaches, reuse fragments of the library code, thus avoiding the need for explicit injection o ..."
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of attack code on the stack. Since the executed code is reused existing code, CRAs bypass current hardware and software security measures that prevent execution from data or stack regions of memory. While softwarebased full control flow integrity (CFI) checking can protect against CRAs, it includes
Abstract Multichannel Communication in Contiki's Low-power IPv6 Stack
"... Vast majority of wireless appliances used in household, industry and medical field share the ISM frequency band. These devices need to coexist and thus are challenged to tolerate their mutual interference. One way of dealing with this is by using frequency hopping; where the device changes its radio ..."
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radio channel periodically. Consequently, communications will not suffer from the same interference each time; instead, it should be fairer and more stable. This thesis investigates the aforementioned problem in the field of low power wireless sensor networks and Internet of Things where Contiki OS
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